w83l950d Winbond Electronics Corp America, w83l950d Datasheet - Page 83

• Manufacturer Part Number: w83l950d
• Description: Peripheral Personal Computer Keyboard Controller
• Manufacturer: Winbond Electronics Corp America

21. SMBUS ADDRESS AND REGISTERS
21.1 SMBus Host Status Register (HSR)
Bit 3: Reserved.
Bit 4: Port 3 PS2 busy
Bit 7-5: Reserved.
BIT
SFR Address 0xA0
Default Value 0x00
Attribute:
7
6
5
4
3
2
1
0
NOT ACK Command Received (NOT_ACK).
1= SMBus controller cannot receive the acknowledge command from the host writing
Receive FIFO Full (RX_FULL).
1= The receive data FIFO has filled 16-bytes data from the SMBus receiver. Write 1 to
Receiver FIFO Time-out (RXTIMEOUT).
1 = If the received data in the FIFO does not over the FIFO threshold level and the time is
SMBus FAILED (FAIL).
1 = The source of the interrupt was a failed bus transaction. This bit is set in response to
SMBus Collision (BUS_COL).
1 = The source of the interrupt was a transaction collision or arbitration fail. Write 1 clear
this bit.
Device Error (DEV_ERR).
1 = Host Device Time-out Error.
Writing 1 to this bit. The micro-controller will then de-assert the interrupt.
REMOTE TX_TIMEOUT (RE_TXTIMEOUT)
1 = When local device is in receiver mode, set this bit to indicate remote device
transmission timeout.
HOST_BUSY (H_BUSY)- Read Only.
1 = SMBus Controller is processing a command from the host interface or receiving
SMBus data.
0 = SMBus controller host interface is not processing a command.
= 0, IDLE
= 1, BUSY
= 0, IDLE
= 1, BUSY
address or data. Write 1 to clear this bit.
clear this bit
over 1 ms, the interrupt also be generated to inform the micro-controller. Perhaps this bit
is always inactive in the polling mode or using package-end status in the interrupt mode.
Write 1 clear this bit. This bit is a source of interrupt.
the KILL bit being set to terminate the host transaction. Write 1 clear this bit.
Read/Write Clear
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DESCRIPTION
W83L950D