w83l950d Winbond Electronics Corp America, w83l950d Datasheet - Page 92

• Manufacturer Part Number: w83l950d
• Description: Peripheral Personal Computer Keyboard Controller
• Manufacturer: Winbond Electronics Corp America

22.2 Auxiliary SMBus Host Control Register (AHCR)
7
6:4
3
2
1
0
Advanced SFR Address 0x29
Default Value
Attribute:
Bit
Reserved.
Baud Rate Select (BAUDRATE). Select SMBus clock baud rate.
This clock is based on Xin or PLL input frequency.
Note: The baud rate of both Master and Slave mode are settled in same bits. When
Enable SMBus Device (EN_SMBUS). Set 1, enable SMBus device.
LAST_BYTE. This bit is used for Host Continue Read Mode.
1 = Software sets this bit to indicate that the next byte will be the last byte to be received
for the data stream. The SMBus controller will send a NOT ACK (instead of an ACK) after
receiving the last byte. Write 0 to disable this function until the last byte is received or
wait the bit of package end status be set to 1.
Host Continue Read Mode (H_CONTRD). This bit is used to determine the control
method for NOT ACK generation when operated on Master-receive mode.
0 = The SMBus controller determines the expected number of data byte for host read by
setting the AH_RBC (Advanced SFR address 2Ah) before a transaction start-off.
1 = The firmware determines when to generate NOT ACK by setting the bit 2
(LAST_BYTE) to 1, in front of the coming last byte.
KILL SMBus (KILL).Set this bit to 1, the data FIFO and SMBus controller device will be
reset and also invoke the bit 4 (FAIL) of HSR set.
Once this bit set, must be cleared to allow the SMBus Host Controller to function
normally.
Note: It is suggested to user don’t reset SMBus via setting this bit.
Set bit 0 of ASCR (Advanced SFR address 033h) is recommended.
operated on Slave mode and deal with a different speed device, the user may resetting
this baud rate for Slave transaction.
BAUDRATE
000
001
010
011
100
101
110
111
Read/Write
0x80
Clock (if 8MHz)
<10K Reserved.
12.5KHz
25KHz
50KHz
200KHz
400KHz
Reserved.
Reserved.
Description
- 83 -
12.5K Hz
25K Hz
50K Hz
100K Hz (Default)
400K Hz
800K Hz
Reserved
Reserved
Clock (if 16MHz)
Publication Release Date: June 23, 2003
W83L950D
Revision 1.0