tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 109

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

Table 1
Register Short Name
A_MFC
A_SRC
A_EXTSLC
A_CHCFG
A_PLLINTC1
A_PLLFRAC0C1
A_PLLFRAC1C1
A_PLLFRAC2C1
A_PLLINTC2
A_PLLFRAC0C2
A_PLLFRAC1C2
A_PLLFRAC2C2
A_PLLINTC3
A_PLLFRAC0C3
A_PLLFRAC1C3
A_PLLFRAC2C3
SFRPAGE
PPCFG0
PPCFG1
PPCFG2
RXRUNCFG0
RXRUNCFG1
CLKOUT0
CLKOUT1
CLKOUT2
RFC
BPFCALCFG0
BPFCALCFG1
XTALCAL0
XTALCAL1
RSSIMONC
ADCINSEL
RSSIOFFS
RSSISLOPE
IM0
IM1
SPMAP
SPMIP
Data Sheet
Register Overview (cont’d)
Register Long Name
Matched Filter Control Register
Sampe Rate Converter NCO Tune
Externel Data Slicer Configuration
PLL MMD Integer Value Register Channel 1
PLL Fractional Division Ratio Register 0 Channel 1 05A
PLL Fractional Division Ratio Register 1 Channel 1 05B
PLL Fractional Division Ratio Register 2 Channel 1 05C
PLL MMD Integer Value Register Channel 2
PLL Fractional Division Ratio Register 0 Channel 2 05E
PLL Fractional Division Ratio Register 1 Channel 2 05F
PLL Fractional Division Ratio Register 2 Channel 2 060
PLL MMD Integer Value Register Channel 3
PLL Fractional Division Ratio Register 0 Channel 3 062
PLL Fractional Division Ratio Register 1 Channel 3 063
PLL Fractional Division Ratio Register 2 Channel 3 064
Special Function Register Page Register
PP0 and PP1 Configuration Register
PP2 and PP3 Configuration Register
PPx Port Configuration Register
RX RUN Configuration Register 0
RX RUN Configuration Register 1
Clock Divider Register 0
Clock Divider Register 1
Clock Divider Register 2
RF Control Register
BPF Calibration Configuration Register 0
BPF Calibration Configuration Register 1
XTAL Coarse Calibration Register
XTAL Fine Calibration Register
RSSI Monitor Configuration Register
ADC Input Selection Register
RSSI Offset Register
RSSI Slope Register
Interrupt Mask Register 0
Interrupt Mask Register 1
Self Polling Mode Active Periods Register
Self Polling Mode Idle Periods Register
Channel Configuration Register
109
Offset Address
03C
03D
03E
058
059
05D
061
080
081
082
083
084
085
086
087
088
089
08A
08B
08C
08D
08E
08F
090
091
094
095
096
097
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Register Overview
V1.0, 2010-02-19
Page Number
136
137
137
138
139
139
140
140
141
141
142
142
143
143
143
144
144
145
146
147
148
149
150
150
151
151
152
152
153
153
154
155
155
156
156
157
157
158
Appendix
TDA5225