tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 127

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tda5225

Manufacturer Part Number
tda5225
Description
Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
Manufacturer
Infineon Technologies Corporation
Datasheet

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Field
WULOT
AFC Limit Configuration Register
A_AFCLIMIT
AFC Limit Configuration Register
Field
UNUSED
AFCLIMIT
AFC/AGC Freeze Delay Register
A_AFCAGCD
AFC/AGC Freeze Delay Register
Field
AFCAGCD
Data Sheet
Bits
4:0
Bits
7:4
3:0
Bits
7:0
Type
w
Type
-
w
Type
w
Description
Wake-Up Level Observation Time
Min. 01h : Twulot = 1 * WULOTPS * 64 / Fsys
Max 1Fh : Twulot = 31 * WULOTPS * 64 / Fsys
Value 00h : Twulot = 32 * WULOTPS * 64 / Fsys
Reset: 00
Description
UNUSED
Reset: 0
AFC Frequency Offset Saturation Limit ==> 1...15 x 21.4 kHz
Min: 1h = +/- Fsys / 2^(22-12) Hz
Max: Fh = +/- 15 * Fsys / 2^(22-12) Hz
Reg. value 0h = 0 Hz - no AFC correction
Reset: 2
Description
AFC/AGC Freeze Delay Counter Division Ratio
The base period for the delay counter is the 8-16 samples/chip
(predecimation strobe) divided by 4
Reset: 00
H
H
H
H
Offset
Offset
02A
02B
127
H
H
Register Description
V1.0, 2010-02-19
Reset Value
Reset Value
Appendix
TDA5225
02
00
H
H

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