tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 115

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

Table 2
Register Short Name
A_WURSSIBL2
A_WURSSIBH2
A_WURSSITH3
A_WURSSIBL3
A_WURSSIBH3
A_WULOT
A_AFCLIMIT
A_AFCAGCD
A_AFCSFCFG
A_AFCK1CFG0
A_AFCK1CFG1
A_AFCK2CFG0
A_AFCK2CFG1
A_PMFUDSF
A_AGCSFCFG
A_AGCCFG0
A_AGCCFG1
A_AGCTHR
A_DIGRXC
A_ISUPFCSEL
A_PDECF
A_PDECSCFSK
A_PDECSCASK
A_MFC
A_SRC
A_EXTSLC
A_CHCFG
A_PLLINTC1
A_PLLFRAC0C1
A_PLLFRAC1C1
A_PLLFRAC2C1
A_PLLINTC2
A_PLLFRAC0C2
A_PLLFRAC1C2
A_PLLFRAC2C2
Data Sheet
Register Overview and Reset Value (cont’d)
Register Long Name
RSSI Wake-Up Blocking Level Low Channel 2
Register
RSSI Wake-Up Blocking Level High Channel 2
Register
RSSI Wake-Up Threshold for Channel 3 Register 021
RSSI Wake-Up Blocking Level Low Channel 3
Register
RSSI Wake-Up Blocking Level High Channel 3
Register
Wake-up on Level Observation Time Register
AFC Limit Configuration Register
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
AFC Integrator 2 Gain Register 1
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
AGC Configuration Register 1
AGC Threshold Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
Pre Decimation Scaling Register FSK Mode
Pre Decimation Scaling Register ASK Mode
Matched Filter Control Register
Sampe Rate Converter NCO Tune
Externel Data Slicer Configuration
PLL MMD Integer Value Register Channel 1
PLL Fractional Division Ratio Register 0 Channel 1 05A
PLL Fractional Division Ratio Register 1 Channel 1 05B
PLL Fractional Division Ratio Register 2 Channel 1 05C
PLL MMD Integer Value Register Channel 2
PLL Fractional Division Ratio Register 0 Channel 2 05E
PLL Fractional Division Ratio Register 1 Channel 2 05F
PLL Fractional Division Ratio Register 2 Channel 2 060
Digital Receiver Configuration Register
Channel Configuration Register
115
Offset Address
01F
020
022
023
025
02A
02B
02C
02D
02E
02F
030
031
032
033
034
035
036
038
039
03A
03B
03C
03D
03E
058
059
05D
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Register Overview
V1.0, 2010-02-19
Reset Value
FF
00
00
FF
00
00
02
00
00
00
00
00
00
42
00
2B
03
08
40
07
00
00
20
07
00
02
44
93
F3
07
09
13
F3
07
09
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Appendix
TDA5225