tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 50

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

The following handling mechanism for read-clear registers was chosen due to
implementation of the Burst Read command:
•
•
Consequence: any interrupt event occurring in the window-time between points A and B
is cleared at point B and not stored/shown in an later readout of ISx.
(However: NINT signal is toggling in any case, if occurring interrupt is not masked in IMx
register)
Figure 27
Please see also the IMPORTANT NOTE in the Burst Read section !
Data Sheet
SFR IS*
SPI IF
the current Interrupt Status (ISx) register 8-bit content is latched into the SPI shift
register after the last address bit is clocked-in (point A in
the IS register is then cleared after last IS register bit is clocked out of the SPI
interface (point B in
nint
ncs
IS(t-1)
irq1 (masked?)
ISx Readout Set Clear Collision
inst
Figure
27)
IS(t+0)
addr
50
A
read/capture IS*
content
read /readb data = IS(t+0)
8-bit @2MHz = 4us
irq2 (masked?)
NOTE:
SFR IS(j) status flag is cleared
before it can be read if an IRQ
occurs during SPI data frame
Figure
IS(t+1) 0x00
Functional Description
B
27)
@end of data frame
SFR IS* read clear
V1.0, 2010-02-19
TDA5225