tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 52

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

To read from the device in Burst mode, the SPI master has to select the SPI slave unit
first. Therefore the master has to drive the NCS line to low. After the instruction byte and
the start address byte have been transferred to the SPI slave (MSB first), the slave unit
will respond by transferring the register contents beginning from the given start address
(MSB first). Driving the NCS line to high will end the Burst frame.
Figure 29
IMPORTANT NOTE - for being upwards compatible with further versions of the
product, we give following strong recommendation:
For read-clear registers at address (N), no read-burst access stopping at address
(N-1) is allowed, because read-clear register will be cleared without being read out.
Use single read command to read out the register at address (N-1) or extend the
burst read to include the read-clear register at address (N).
To write to the device, the SPI master has to select the SPI slave unit first. Therefore,
the master must set the NCS line to low. After this, the instruction byte and the address
byte are shifted in on SDI and stored in the internal instruction and address register. The
following data byte is then stored at this address.
After completing the writing operation, the master sets the NCS line to high.
Additionally the received address byte is stored into the register SPIAT and the received
data byte is stored into the register SPIDT. These two trace registers are readable.
Therefore, an external controller is able to check the correct address and data
transmission by reading out these two registers after each write instruction. The trace
Data Sheet
NCS
SCK
SDO
SDI
high impedance Z
I7 I6
1
I5 I4
Instruction
I3 I2
Burst Read Registers
I1 I0
8
A7 A6
1
Register Start Address
A5 A4
A3 A2 A1 A0
8
D7 D6 D5 D4
1
Data Out (i)
D3 D2 D1
52
D0 D7 D6 D5 D4 D3 D2 D1 D0
8
1
Data Out (i+1)
8
D7
Functional Description
D0
D7 D6 D5 D4 D3 D2 D1 D0
1
Data Out (i+x)
V1.0, 2010-02-19
TDA5225
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