tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 114

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

Table 1
Register Short Name
D_AFCK2CFG1
D_PMFUDSF
D_AGCSFCFG
D_AGCCFG0
D_AGCCFG1
D_AGCTHR
D_DIGRXC
D_ISUPFCSEL
D_PDECF
D_PDECSCFSK
D_PDECSCASK
D_MFC
D_SRC
D_EXTSLC
D_CHCFG
D_PLLINTC1
D_PLLFRAC0C1
D_PLLFRAC1C1
D_PLLFRAC2C1
D_PLLINTC2
D_PLLFRAC0C2
D_PLLFRAC1C2
D_PLLFRAC2C2
D_PLLINTC3
D_PLLFRAC0C3
D_PLLFRAC1C3
D_PLLFRAC2C3
Table 2
Register Short Name
Appendix - Registers
A_IF1
A_WURSSITH1
A_WURSSIBL1
A_WURSSIBH1
A_WURSSITH2
Data Sheet
Register Overview (cont’d)
Register Overview and Reset Value
Chapter,
Register Long Name
AFC Integrator 2 Gain Register 1
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
AGC Configuration Register 1
AGC Threshold Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
Pre Decimation Scaling Register FSK Mode
Pre Decimation Scaling Register ASK Mode
Matched Filter Control Register
Sampe Rate Converter NCO Tune
Externel Data Slicer Configuration
PLL MMD Integer Value Register Channel 1
PLL Fractional Division Ratio Register 0 Channel 1 35A
PLL Fractional Division Ratio Register 1 Channel 1 35B
PLL Fractional Division Ratio Register 2 Channel 1 35C
PLL MMD Integer Value Register Channel 2
PLL Fractional Division Ratio Register 0 Channel 2 35E
PLL Fractional Division Ratio Register 1 Channel 2 35F
PLL Fractional Division Ratio Register 2 Channel 2 360
PLL MMD Integer Value Register Channel 3
PLL Fractional Division Ratio Register 0 Channel 3 362
PLL Fractional Division Ratio Register 1 Channel 3 363
PLL Fractional Division Ratio Register 2 Channel 3 364
Register Long Name
RSSI Wake-Up Threshold for Channel 1 Register 01B
RSSI Wake-Up Blocking Level Low Channel 1
Register
RSSI Wake-Up Blocking Level High Channel 1
Register
RSSI Wake-Up Threshold for Channel 2 Register 01E
Digital Receiver Configuration Register
Channel Configuration Register
IF1 Register
Register Description
114
Offset Address
330
331
332
333
334
335
336
338
339
33A
33B
33C
33D
33E
358
359
35D
361
Offset Address
016
01C
01D
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Register Overview
V1.0, 2010-02-19
Page Number
Reset Value
20
00
FF
00
00
H
H
H
H
H
Appendix
TDA5225