pxb4340e Infineon Technologies Corporation, pxb4340e Datasheet - Page 114

• Manufacturer Part Number: pxb4340e
• Description: Atm Oam Processor Aop
• Manufacturer: Infineon Technologies Corporation

Data Sheet
Bit 31
CTSDCID(6:0)
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
PAR
Dword parity protection. In normal operation write to 0. Should always
read as 0.
Identifier for Data Collection on terminated / intermediate F5 Segment
BR cells. Related enable is CTSDCEN in Dword3.
CLOCF2N
1
CLOCD2F
1
CRDIF2N
1
CRDID2F
1
CAISF2N
1
CAISD2F
1
EDCERR
1
Indication for a state transition from F5 LOC failure state
to F5 LOC normal state. Set by AOP, reset by the µP.
Reported with interrupt DCSTTR if enabled with
CAISMEN=1 (Dword1).
Indication for a state transition from F5 LOC defect state
to F5 LOC failure state. Set by AOP, reset by the µP.
Reported with interrupt DCSTTR if enabled with
CCCMEN=1 (Dword1).
Indication for a state transition from F5 RDI failure state to
F5 RDI normal state. Set by AOP, reset by the µP.
Reported with interrupt DCSTTR if enabled with
CRDIMEN (Dword1).
Indication for a state transition from F5 RDI defect state to
F5 RDI failure state. Set by AOP, reset by the µP.
Reported with interrupt DCSTTR if enabled with
CRDIMEN=1. (Dword1.
Indication for a state transition from F5 AIS failure state to
F5 AIS normal state. Set by AOP, reset by the
µP.Reported with interrupt DCSTTR if enabled with
CAISMEN=1 (Dword1).
Indication for a state transition from F5 AIS defect state to
F5 AIS failure state. Set by AOP, reset by the µP.
Reported
CAISMEN=1 (Dword1).
Wrong EDC (CRC10) in an OAM cell detected. Reported
with interrupt DEDCER.
3-114
with
interrupt
DCSTR
if
enabled
04.2000
with