pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 120

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 36
Mode
Interrupt enable
register
latch_on_reset
Read/write
self clearing
4.1.1
Command Register
CMDR
Command Register
Field
RRES
XRES
Data Sheet
Registers Access Types (cont’d)
Control Registers
Bits
6
4
Symbol Description Hardware (HW)
ien
lor
rwsc
Enables the interrupt source for
interrupt generation
rw register, value is latched after first
clock cycle after reset
Register is used as input for the HW,
the register will be cleared due to a HW
mechanism.
Type
w
w
Description
Receiver Reset
The receive line interface except the clock and data recovery unit (DPLL)
is reset. However the contents of the control registers is not deleted.
A receiver reset should be made after switching from power down to
power up (GCR.PD = ´1´ -> ´0´).
Transmitter Reset
The transmit framer and transmit line interface excluding the system
clock generator and the pulse shaper are reset. However the contents of
the control registers is not deleted.
Offset
xx02
120
H
Description Software (SW)
SW can read and write this register
Register is read and writable by SW
Writing to the register generates a strobe
signal for the HW (1 pdi clock cycle)
Register is read and writable by SW.
Register DescriptionCommand Register
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Reset Value
00
TM
H