pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 198

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Line Status Register 1
LSR1
Line Status Register 1
Field
EXZD
PDEN
LLBDD
LLBAD
Data Sheet
Bits
7
6
4
3
Type
r
r
r
r
Description
Excessive Zeros Detected
Significant only, if excessive zero detection has been enabled
(MR0.EXZE = ´1´). Set after detection of more than 3 (HDB3 code) or 15
(AMI code) contiguous zeros in the received data stream.This bit is
cleared on read.
Pulse-Density Violation Detected
The pulse-density of the received data stream is below the requirement
defined by ANSI T1. 403 or more than 14 consecutive zeros are detected.
With the violation of the pulse-density this bit is set and remains active
until the pulse-density requirement is fulfilled for 23 consecutive "1"-
pulses. Additionally an interrupt status ISR0.PDEN is generated with the
rising edge of PDEN.
Line Loop-Back Deactivation Signal Detected, only valid in T1 mode
In E1 mode the equivalent bit is LSR2.LLBDD.
This bit is set in case of the LLB deactivate signal is detected and then
received over a period of more than 33,16 ms with a bit error rate less
than 10
10
into account for the error rate calculation.Any change of this bit causes an
LLBSC interrupt.
Line Loop-Back Activation Signal Detected, only valid in T1 mode
In E1 mode the equivalent bit is LSR2.LLBAD.
Depending on bit LCR1.EPRM the source of this status bit changed.
•
•
-2
LCR1.EPRM = ´0´: This bit is set in case of the LLB activate signal is
detected and then received over a period of more than 33,16 ms with
a bit error rate less than 10
error rate does not exceed 10
position of any frame is not taken into account for the error rate
calculation. Any change of this bit causes an LLBSC interrupt.
LCR1.EPRM = ´1´: The current status of the PRBS synchronizer is
indicated in this bit. It is set high if the synchronous state is reached
even in the presence of a bit error rate of up to 10
containing all zeros or all ones with/without framing bits is also a valid
pseudo-random binary sequence.
. If framing is aligned, the first bit position of any frame is not taken
-2
. The bit remains set as long as the bit error rate does not exceed
Offset
xx4D
198
H
Register DescriptionLine Status Register 1
-2
. The bit remains set as long as the bit
-2
. If framing is aligned, the first bit
Rev. 1.3, 2006-01-25
-3
. A data stream
QuadLIU
PEF 22504
Reset Value
xx
TM
H