pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 23

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 1
Pin No.
J13
L4
J11
J12
M4
Data Sheet
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
WR
RW
DBW
BHE
BLE
CS
INT
Pin Type Buffer
I
I
I
I
I
I
O
Type
PU
PU
PU
PU
PU
PU
–
23
Function
Write Enable
Intel bus mode.
This signal indicates a write operation. When CS is
active the QuadLIU
data provided on the data bus.
Read/Write Select
Motorola bus mode.
This signal distinguishes between read and write
operation.
Data Bus Width select
Bus interface mode
A low signal on this input selects the 8-bit bus interface
mode. A high signal on this input selects the 16-bit bus
interface mode. In this case word transfer to/from the
internal registers is enabled. Byte transfers are
implemented by using A0 and BHE/BLE.
Bus High Enable
Intel bus mode.
If 16-bit bus interface mode is enabled, this signal
indicates a data transfer on the upper byte of the data
bus D(15:8). In 8-bit bus interface mode this signal has
no function and should be tied to VDD or left open.
Bus Low Enable
Motorola bus mode.
If 16-bit bus interface mode is enabled, this signal
indicates a data transfer on the lower byte of the data
bus D(7:0). In 8-bit bus interface mode this signal has
no function and should be tied to VDD or left open.
Chip Select
Low active chip select.
Interrupt Request
Interrupt request.
INT serves as general interrupt request for all interrupt
sources. These interrupt sources can be masked via
registers IMR(7:0). Interrupt status is reported via
registers GIS (Global Interrupt Status) and ISR(7:0).
Output characteristics (push-pull active low/high, open
drain) are determined by programming register IPC.
TM
loads an internal register with
Rev. 1.3, 2006-01-25
Pin Descriptions
QuadLIU
PEF 22504
TM