pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 216

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pef22504

Manufacturer Part Number
pef22504
Description
Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
Manufacturer
Infineon Technologies Corporation
Datasheet
Interrupt Status Register 7
All bits are reset when ISR7 is read. If bit GCR.VIS is set, interrupt statuses in ISR7 are flagged although they are
masked by register IMR7. However, these masked interrupt statuses neither generate a signal on INT, nor are
visible in register GIS, see
ISR7
Interrupt Status Register 7
Field
XCLKSS1
XCLKSS0
Data Sheet
Bits
4
3
Chapter
Type
rsc
rsc
3.5.3.
Description
XCLK Source Switched 1
See
reference between TCLK and FCLKX was performed. If automatically
switching is not enabled (CMR6.ATCS = ´0´), this bit is always ´0´. Note
that the status of TCLK is shown independent on CMR6.ATC in
CLKSTAT.TCLKLOS.
0
1
XCLK Source Switched 0
See
source between TCLK and DCO-X output was performed. If automatically
switching is not enabled (CMR6.ATCS = ´0´), this bit is always ´0´. Note
that the status of TCLK is shown independent on CMR6.ATC in
CLKSTAT.TCLKLOS.
0
1
B
B
B
B
Chapter
Chapter
XCLK is always sourced by the DCO-X output.
output in case of TCLK loss or automatically switched back from
DCO-X output to TCLK in case that TCLK is active again. The
DCO-X is always sourced by FCLKX.
DCO-X reference not switched.
DCO-X reference has switched between TCLK and FCLKX. The
XCLK source not switched.
XCLK source has switched automatically from TCLK to DCO-X
Offset
xxD8
3.9.3. Shows if an automatically switching of the DCO-X
3.9.3. Shows if an automatically switching of the XCLK
216
H
Register DescriptionInterrupt Status Register 7
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Reset Value
00
TM
H

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