pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 210

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Interrupt Status Register 4
All bits are reset when ISR4 is read. If bit GCR.VIS is set, interrupt statuses in ISR4 are flagged although they are
masked by register IMR4. However, these masked interrupt statuses neither generate a signal on INT, nor are
visible in register GIS, see
ISR4
Interrupt Status Register 4
Field
XSP
XSN
Data Sheet
Bits
7
6
Chapter
Type
rsc
rsc
3.5.3.
Description
Transmit Slip Positive
The frequency of the transmit clock is less than the frequency of the
transmit system interface working clock based on 2.048 MHz. A frame is
repeated. After a slip has performed writing of register XC1 is not
necessary.
Transmit Slip Negative
The frequency of the transmit clock is greater than the frequency of the
transmit system interface working clock based on 2.048 MHz. A frame is
skipped. After a slip has performed writing of register XC1 is not
necessary.
Offset
xx6C
210
H
Register DescriptionInterrupt Status Register 4
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Reset Value
00
TM
H