pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 60

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 2
Pin No.
120
121
122
123
120
121
122
123
120
121
122
123
120
121
122
123
120
121
122
123
120
121
122
123
120
121
122
123
Data Sheet
Name
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
I/O Signals for P-TQFP-144-8 (cont’d)
Pin Type
I
O
O
O
O
I
I
Buffer
Type
PU
–
–
–
–
PU
PU
Function
Transmit Clock (TCLK) input, port 1
PC(1:4).XPC(3:0) = 0011
A 2.048/8.192 MHz (E1) or 1.544/6.176 MHz (T1/J1) clock
has to be sourced by the system if the internally generated
transmit clock (generated by DCO-X) shall not be used.
Optionally this input is used as a synchronization clock for the
DCO-X circuitry with a frequency of 2.048 (E1) or 1.544 MHz
(T1/J1).
Transmit Multiframe Begin (XMFB), port 1
PC(1:4).XPC(3:0) = 0100
XMFB marks the beginning of every transmitted multiframe
on XDI. The signal is active high for one 2.048 (E1) or
1.544 MHz (T1/J1) period.
Transmit Signaling Marker (XSIGM), port 1
PC(1:4).XPC(3:0) = 0101
E1
Marks the transmit time slots on XDI of every frame which are
defined by register TTR(1:4).
T1/J1
Marks the transmit time slots on XDI of every frame which are
defined by register TTR(1:4) (if not CAS-BR is used).
When using the CAS-BR signaling scheme the robbed bit of
each channel in every sixth frame is marked.
Data Link Bit Transmit (DLX), port 1
PC(1:4).XPC(3:0) = 0110
E1
Marks the Sa(8:4)-bits within the data stream on XDI. The
Sa(8:4)-bit positions in time slot 0 of every frame not
containing the frame alignment signal are selected by
register XC0.SA8E to XC0.SA4E.
T1/J1
This output provides a 4 kHz signal which marks the DL-bit
position within the data stream on XDI (in ESF mode only).
Tran4mit Clock (XCLK), port 1
PC(1:4).XPC(3:0) = 0111
Transmit line clock of 2.048 MHz (E1) or 1.544 MHz (T1/J1)
derived from SCLKX/R, RCLK or generated internally by
DCO circuitries.
Transmit Line Tristate (XLT), port 1
PC(1:4).XPC(3:0) = 1000
A high level on this port sets the transmit lines XL1/2 or
XDOP/N into tristate mode. This pin function is logically ored
with register bit XPM2.XLT.
General Purpose Input (GPI), port 1
PC(1:4).XPC(3:0) = 1001
The pin is set to input. The state of this input is reflected in
the register bits MFPI.XPA, MFPI.XPB or MFPI.XPC
respectively.
60
B
B
B
B
B
B
B
.
Rev. 1.3, 2006-01-25
Pin Descriptions
QuadLIU
PEF 22504
TM