psd813f1a-90ut STMicroelectronics, psd813f1a-90ut Datasheet - Page 21

• Manufacturer Part Number: psd813f1a-90ut
• Description: Flash In-system Programmable Isp Peripherals For 8-bit Mcus
• Manufacturer: STMicroelectronics

20
PSD913F1
The
PSD913F1
Functional
Blocks
(cont.)
9.1.1.5.4 Read the OTP Row
There are 64 bytes of One-Time-Programmable (OTP) memory that reside in EEPROM.
These 64 bytes are in addition to the 32 Kbytes of EEPROM memory. A read of the
OTP row is done with an instruction composed of at least 4 operations: 3 specific write
operations and one to 64 read operations (see Table 9). During the read operation(s),
address bit A6 must be zero, while address bits A5-A0 define the OTP Row byte to be read
while any EEPROM sector select signal (EESi) is active. After reading the last byte, an
EEPROM Return instruction must be executed (see Table 9).
9.1.1.5.5 Read the Erase/Program Status Bits
The PSD913F1 provides several status bits to be used by the microcontroller to confirm
the completion of an erase or programming instruction of Flash memory. Bits are also
available to show the status of writes to EEPROM. These status bits minimize the time that
the microcontroller spends performing these tasks and are defined in Table 10. The status
bits can be read as many times as needed.
Table 10. Status Bit
NOTES: 1. X = Not guaranteed value, can be read either 1 or 0.
For Flash memory, the microcontroller can perform a read operation to obtain these status
bits while an erase or program instruction is being executed by the embedded algorithm.
See section 9.1.1.7 for details.
For EEPROM not in SDP mode, the microcontroller can perform a read operation to obtain
these status bits just after a data write operation. The microcontroller may write one to 64
bytes before reading the status bits. See section 9.1.1.6 for details.
For EEPROM in SDP mode, the microcontroller will perform a read operation to obtain
these status bits while an SDP write instruction is being executed by the embedded
algorithm. See section 9.1.1.1.3 for details.
Flash
EEPROM
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FSi and EESi are active high.
CSBOOTi
FSi/
V
V
IH
IL
EESi
V
V
IH
IL
Polling
Polling
Data
Data
DQ7
Toggle Error
Toggle
Flag
Flag
DQ6
DQ5
Flag
X
DQ4
X
X
Erase
Time-
DQ3
out
X
DQ2
X
X
DQ1
X
X
Preliminary
DQ0
X
X