psd813f1a-90ut STMicroelectronics, psd813f1a-90ut Datasheet - Page 78

• Manufacturer Part Number: psd813f1a-90ut
• Description: Flash In-system Programmable Isp Peripherals For 8-bit Mcus
• Manufacturer: STMicroelectronics

PLD Combinatorial Timing
Preliminary
Microcontroller Interface – PSD913F1V AC/DC Parameters
(3.0 V to 3.6 V Versions)
Write, Erase and Program Timing
NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
NOTES: 1. Any input used to select an internal PSD913F1 function.
Symbol
t
t
Symbol
PD
ARD
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LVLX
AVLX
LXAX
AVWL
WHAX 1
WHAX2
WHPV
WLMV
DVMV
AVPV
SLWL
DVWH
WHDX
WLWH
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active write signal.
5. Assuming write is active before data becomes valid.
6. Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
PLD Input Pin/Feedback to
PLD Combinatorial Output
PLD Array Delay
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Leading
Edge of WR
CS Valid to Leading Edge of WR
WR Data Setup Time
WR Data Hold Time
WR Pulse Width
Trailing Edge of WR to Address Invalid
Trailing Edge of WR to DPLD Address
Input Invalid
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
WR Valid to Port Output Valid Using
Micro Cell Register Preset/Clear
Data Valid to Port Output Valid
Using Micro Cell Register Preset/Clear
Address Input Valid to Address
Output Delay
Parameter
Parameter
(3.0 V to 3.6 V Versions)
(3.0 V to 3.6 V Versions)
Conditions
(Note 1)
(Note 1)
(Notes 1 and 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Notes 3 and 6)
(Note 3)
(Notes 3 and 4)
(Notes 3 and 5)
(Note 2)
Conditions
Min
-15
Max
48
29
Min
-20
Min
26
10
12
20
20
45
48
12
8
0
Max
-15
55
33
Max
45
48
90
90
Add 20 Sub 6
TURBO
OFF
Min
30
12
14
25
25
50
10
53
17
0
-20
(Note 1)
Slew
Max
100
100
50
55
PSD913F1
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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