psd813f1a-90ut STMicroelectronics, psd813f1a-90ut Datasheet - Page 61

• Manufacturer Part Number: psd813f1a-90ut
• Description: Flash In-system Programmable Isp Peripherals For 8-bit Mcus
• Manufacturer: STMicroelectronics

The
PSD913F1
Functional
Blocks
(cont.)
60
PSD913F1
9.5.2 Other Power Saving Options
The PSD913F1 offers other reduced power saving options that are independent of the
Power Down Mode. Except for the SRAM Standby and CSI input features, they are enabled
by setting bits in the PMMR0 and PMMR2 registers.
9.5.2.1 Zero Power PLD
The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0. By
setting the bit to “1”, the Turbo mode is disabled and the PLDs consume Zero Power
current when the inputs are not switching for an extended time of 70 ns. The propagation
delay time will be increased by 10 ns after the Turbo bit is set to “1” (turned off) when the
inputs change at a composite frequency of less than 15 MHz. When the Turbo bit is set to a
“0” (turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD’s D.C.
power, AC power, and propagation delay.
Note: Blocking MCU control signals with PMMR2 bits can further reduce PLD AC power
consumption.
9.5.2.2 SRAM Standby Mode (Battery Backup)
The PSD913F1 supports a battery backup operation that retains the contents of the SRAM
in the event of a power loss. The SRAM has a Vstby pin (PC2) that can be connected to an
external battery. When V
connect to Vstby as a power source to the SRAM. The SRAM Standby Current (Istby) is
typically 0.5 µA. The SRAM data retention voltage is 2 V minimum. The battery-on indicator
(Vbaton) can be routed to PC4. This signal indicates when the V
Vstby voltage.
9.5.2.3 The CSI Input
Pin PD2 of Port D can be configured in PSDsoft as the CSI input. When low, the signal
selects and enables the internal Flash, EEPROM, SRAM, and I/O for read or write
operations involving the PSD913F1. A high on the CSI pin will disable the Flash memory,
EEPROM, and SRAM, and reduce the PSD power consumption. However, the PLD and I/O
pins remain operational when CSI is high. Note: there may be a timing penalty when using
the CSI pin depending on the speed grade of the PSD that you are using. See the timing
parameter t
9.5.2.4 Input Clock
The PSD913F1 provides the option to turn off the CLKIN input to the PLD AND array to
save AC power consumption. During Power Down Mode, or, if the CLKIN input is not being
used as part of the PLD logic equation, the clock should be disabled to save AC power. The
CLKIN will be disconnected from the PLD AND array by setting bits 4 to a “1” in PMMR0.
9.5.2.5 Input Control Signals
The PSD913F1 provides the option to turn off the input control signals (CNTL0-2, ALE, and
DBE) to the PLD to save AC power consumption. These control signals are inputs to the
PLD AND array. During Power Down Mode, or, if any of them are not being used as part of
the PLD logic equation, these control signals should be disabled to save AC power. They
will be disconnected from the PLD AND array by setting bits 2, 3, 4, 5, and 6 to a “1” in the
PMMR2.
Table 28. APD Counter Operation
Enable Bit
APD
0
1
1
1
SLQV
PD Polarity
in the AC/DC specs.
ALE
X
X
1
0
CC
becomes lower than Vstby then the PSD will automatically
ALE Level
Pulsing
X
1
0
Not Counting
Not Counting
Counting (Generates PDN after 15 Clocks)
Counting (Generates PDN after 15 Clocks)
APD Counter
CC
has dropped below the
Preliminary