psd813f1a-90ut STMicroelectronics, psd813f1a-90ut Datasheet - Page 60

• Manufacturer Part Number: psd813f1a-90ut
• Description: Flash In-system Programmable Isp Peripherals For 8-bit Mcus
• Manufacturer: STMicroelectronics

Preliminary
The
PSD913F1
Functional
Blocks
(cont.)
Table 27. Power Management Mode Registers (PMMR0, PMMR2)**
PMMR0
***
***
***
PMMR2
*
Bit 2 0 = Cntl0 input to the PLD AND array is connected.
Bit 3 0 = Cntl1 input to the PLD AND array is connected.
Bit 4 0 = Cntl2 input to the PLD AND array is connected.
Bit 5 0 = ALE input to the PLD AND array is connected.
Bit 6 0 = DBE input to the PLD AND array is connected.
Bit 1 0 = Automatic Power Down (APD) is disabled.
Bit 3 0 = PLD Turbo is on.
Bit 4 0 = CLKIN input to the PLD AND array is connected.
Unused bits should be set to 0.
Bits 0, 2, 6, and 7 are not used, and should be set to 0, bit 5 should be set to 1.
The PMMR0, and PMMR2 register bits are cleared to zero following power up.
Subsequent reset pulses will not clear the registers.
Bit 7
Bit 7
*
*
1 = Cntl0 input to PLD AND array is disconnected, saving power.
1 = Cntl1 input to PLD AND array is disconnected, saving power.
1 = Cntl2 input to PLD AND array is disconnected, saving power.
1 = ALE input to PLD AND array is disconnected, saving power.
1 = DBE input to PLD AND array is disconnected, saving power.
1 = Automatic Power Down (APD) is enabled.
1 = PLD Turbo is off, saving power.
1 = CLKIN input to PLD AND array is disconnected, saving power.
Every CLKIN change will power up the PLD when Turbo bit is off.
1 = off
Bit 6
array
Bit 6
DBE
PLD
*
1 = off
Bit 5
array
Bit 5
PLD
ALE
*
Array clk
CNTL2
1 = off
1 = off
Bit 4
array
Bit 4
PLD
PLD
CNTL1
1 = off
1 = off
Turbo
Bit 3
array
Bit 3
PLD
PLD
CNTL0
1 = off
Bit 2
array
Bit 2
PLD
*
Enable
1 = on
Bit 1
Bit 1
APD
*
PSD913F1
Bit 0
Bit 0
*
*
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