hyb18t512160b2fl-5 Qimonda, hyb18t512160b2fl-5 Datasheet - Page 14

• Manufacturer Part Number: hyb18t512160b2fl-5
• Description: 512-mbit Double-data-rate-two Sdram
• Manufacturer: Qimonda

2.2
The chip configuration of a DDR2 SDRAM is listed by function in
columns are explained in
Rev. 1.40, 2008-03
10062006-YPTZ-CDR7
Ball#
Clock Signals ×16 Organization
J8
K8
K2
Control Signals ×16 Organization
K7
L7
K3
L8
Address Signals ×16 Organization
L2
L3
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
Name
CK
CK
CKE
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
Configuration for TFBGA-84
Table 8
Ball
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
and
Table 9
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
respectively.
Function
Clock Signal CK, CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Chip Select
Bank Address Bus 1:0
Address Signal 12:0, Address Signal 10/Autoprecharge
14
Table
7. The abbreviations used in the Ball#/Buffer Type
512-Mbit Double-Data-Rate-Two SDRAM
HY[B/I]18T512[40/80/16]0B2[C/F](L)
Internet Data Sheet
Configuration
TABLE 7