hyb18t512160b2fl-5 Qimonda, hyb18t512160b2fl-5 Datasheet - Page 3

• Manufacturer Part Number: hyb18t512160b2fl-5
• Description: 512-mbit Double-data-rate-two Sdram
• Manufacturer: Qimonda

1
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• 1.8 V
• DRAM organizations with 4,8,16 data in/outputs
• Double Data Rate architecture:
• Programmable CAS Latency: 3, 4, 5 and 6
• Programmable Burst Length: 4 and 8
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are
• DLL aligns DQ and DQS transitions with clock
• DQS can be disabled for single-ended data strobe
• Commands entered on each positive clock edge, data and
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better
Rev. 1.40, 2008-03
10062006-YPTZ-CDR7
1.8 V
– two data transfers per clock cycle
– four internal banks for concurrent operation
transmitted / received with data. Edge aligned with read
data and center-aligned with write data.
operation
data mask are referenced to both edges of DQS
command and data bus efficiency
±
±
0.1 V Power Supply
0.1 V (SSTL_18) compatible I/O
Overview
Features
3
• Off-Chip-Driver impedance adjustment (OCD) and
• Auto-Precharge operation for read and write bursts
• Auto-Refresh, Self-Refresh and power saving Power-
• Operating temperature range 0 °C to 95 °C
• Industrial temperature range -40 °C to 95 °C
• Average Refresh Period 7.8 μs at a
• Programmable self refresh rate via EMRS2 setting
• Programmable partial array refresh via EMRS2 settings
• DCC enabling via EMRS2 setting
• Full and reduced Strength Data-Output Drivers
• 1KB page size for ×4 and ×8, 2KB page size for ×16
• Packages: PG-TFBGA-60, PG-TFBGA-84, P-TFBGA-60,
• All Speed grades faster than DDR2–400 comply with
On-Die-Termination (ODT) for better signal quality
Down modes
than 85 °C, 3.9 μs between 85 °C and 95 °C
P-TFBGA-84
DDR2–400 timing specifications when run at a clock rate
of 200 MHz.
512-Mbit Double-Data-Rate-Two SDRAM
HY[B/I]18T512[40/80/16]0B2[C/F](L)
Internet Data Sheet
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