hyb18t512160b2fl-5 Qimonda, hyb18t512160b2fl-5 Datasheet - Page 44

• Manufacturer Part Number: hyb18t512160b2fl-5
• Description: 512-mbit Double-data-rate-two Sdram
• Manufacturer: Qimonda

1)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
5) Inputs are not recognized as valid until
6) The output timing reference voltage level is
7) New units, ‘
Rev. 1.40, 2008-03
10062006-YPTZ-CDR7
Parameter
Mode register set command cycle
time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Read preamble
Read postamble
Active to active command period for
1KB page size products
Active to active command period for
2KB page size products
Internal Read to Precharge command
delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit active power down to read
command
Exit active power down to read
command (slow exit, lower power)
Exit precharge power-down to any
command
Exit self-refresh to a non-read
command
Exit self-refresh to read command
Write command to DQS associated
clock edges
V
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode. DQS RDQS
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x
DDQ
= 1.8 V ± 0.1V;
t
CK.AVG
t
CK
‘ is used for both concepts. Example:
‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘
V
DD
= 1.8 V ± 0.1 V.
V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WL
REF
MRD
OIT
QH
QHS
REFI
RFC
RPRE
RPST
RRD
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
V
stabilizes. During the period before
TT
.
DDR2–800
2
0
t
—
—
—
105
0.9
0.4
7.5
10
7.5
0.35
0.4
15
7.5
2
8 – AL
2
t
200
RL – 1
t
Min.
HP
RFC
XP
= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
–
t
+10
CK.AVG
t
QHS
+
44
t
ERR.2PER(Min)
Max.
—
12
—
300
7.8
3.9
—
1.1
0.6
—
—
—
—
0.6
—
—
—
—
—
—
—
.
V
t
REF
CK.AVG
DDR2–667
2
0
t
—
—
—
105
7.5
10
7.5
0.35
15
7.5
2
7 – AL
2
t
200
RL–1
0.9
0.4
0.4
512-Mbit Double-Data-Rate-Two SDRAM
Min.
HP
RFC
stabilizes, CKE = 0.2 x
–
‘ represents the actual
+10
t
HY[B/I]18T512[40/80/16]0B2[C/F](L)
QHS
Max.
—
12
—
340
7.8
3.9
—
1.1
0.6
—
—
—
—
0.6
—
—
—
—
—
—
—
V
DDQ
t
Internet Data Sheet
CK.AVG
is recognized as low.
Unit
nCK
ns
ps
ps
μs
μs
ns
t
t
ns
ns
ns
t
t
ns
ns
nCK
nCK
nCK
ns
nCK
nCK
CK.AVG
CK.AVG
CK.AVG
CK.AVG
of the input clock
Note
)4)5)6)7)
34)
25)
26)
27)28)
27)29)
30)
31)32)
31)33)
34)
34)
34)
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34)35)
34)
1)2)3