hyb18t512160bf-5 Infineon Technologies Corporation, hyb18t512160bf-5 Datasheet - Page 13

• Manufacturer Part Number: hyb18t512160bf-5
• Description: 240-pin Unbuffered Ddr2 Sdram Modules
• Manufacturer: Infineon Technologies Corporation

Table 6
Pin or Ball No.
162
167
168
Data Strobe Bus
7
16
28
37
84
93
105
114
46
6
15
27
36
83
92
104
113
45
Data Sheet
Pin Configuration of UDIMM (cont’d)
Name Pin
CB5
NC
CB6
NC
CB7
NC
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
DQS5 I/O
DQS6 I/O
DQS7 I/O
DQS8 I/O
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
DQS5 I/O
DQS6 I/O
DQS7 I/O
DQS8 I/O
Type
I/O
NC
I/O
NC
I/O
NC
Buffer
Type
SSTL
—
SSTL
—
SSTL
—
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Check Bit 5
Note: ECC type module only
Not Connected
Note: ECC type module only
Check Bit 6
Note: ECC type module only
Not Connected
Note: ECC type module only
Check Bit 7
Note: ECC type module only
Not Connected
Note: Non-ECC module
Data Strobe Bus 8:0
The data strobes, associated with one data byte, sourced with data
transfers. In Write mode, the data strobe is sourced by the controller
and is centered in the data window. In Read mode the data strobe is
sourced by the DDR2 SDRAM and is sent at the leading edge of the
data window. DQS signals are complements, and timing is relative to
the crosspoint of respective DQS and DQS. If the module is to be
operated in single ended strobe mode, all DQS signals must be tied
on the system board to
programmed appropriately.
Note: See block diagram for corresponding DQ signals
Complement Data Strobe Bus 8:0
Note: See block diagram for corresponding DQ signals
13
HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A
V
Unbuffered DDR2 SDRAM Modules
SS
and DDR2 SDRAM mode registers
Pin Configuration and Block Diagrams
02182004-DHQB-4RRW
Rev. 1.3, 2005-09