hyb18t512160bf-5 Infineon Technologies Corporation, hyb18t512160bf-5 Datasheet - Page 35

• Manufacturer Part Number: hyb18t512160bf-5
• Description: 240-pin Unbuffered Ddr2 Sdram Modules
• Manufacturer: Infineon Technologies Corporation

Table 24
Parameter
Data hold skew factor
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh command period
Precharge-All (4 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command period
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-Precharge
Write recovery time for write with Auto-Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read command (slow
exit, lower power)
Exit precharge power-down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
1) For details and notes see the relevant INFINEON component data sheet
2)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
6) Inputs are not recognized as valid until
7) The output timing reference voltage level is
8) 0 ≤
9) 85 °C <
10) x4 & x8
11) x16
Data Sheet
V
powered down and then restarted through the specified initialization sequence before normal operation can continue.
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode
recognized as low.
DDQ
T
CASE
= 1.8 V ± 0.1 V;
T
CASE
≤ 85 °C
Timing Parameter by Speed Grade - DDR2-400
≤ 95 °C
V
DD
= 1.8 V ± 0.1 V. See notes
V
REF
V
stabilizes. During the period before
TT
. See Chapter 8 for the reference load for timing measurements.
4)5)6)7)
35
Symbol
t
t
t
t
t
t
t
t
t
t
t
WR
t
t
t
t
t
t
QHS
REFI
RFC
RP
RPRE
RPST
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A
Unbuffered DDR2 SDRAM Modules
DDR2-400
Min.
—
—
—
75
t
0.9
0.40
7.5
10
7.5
0.35
0.40
10
t
7.5
2
6 – AL
2
t
200
RP
WR
RFC
/
+ 1
t
CK
+10
V
t
REF
CK
stabilizes, CKE = 0.2 x
Max.
450
7.8
3.9
—
—
1.1
0.60
—
—
—
—
0.60
—
—
—
—
—
—
—
Electrical Characteristics
02182004-DHQB-4RRW
Unit
ps
µs
µs
ns
ns
t
t
ns
ns
ns
t
t
ns
t
ns
t
t
t
ns
t
Rev. 1.3, 2005-09
CK
CK
CK
CK
CK
CK
CK
CK
CK
V
Note
1)2)3)4)5)6)7)
8)
9)
10)
11)
DDQ
is