hyb18t512160bf-5 Infineon Technologies Corporation, hyb18t512160bf-5 Datasheet - Page 28

• Manufacturer Part Number: hyb18t512160bf-5
• Description: 240-pin Unbuffered Ddr2 Sdram Modules
• Manufacturer: Infineon Technologies Corporation

Table 19
Speed Grade
IFX Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
Table 20
Speed Grade
IFX Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
Data Sheet
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode
recognized as low.
t
equal to 9 x
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode
recognized as low.
t
equal to 9 x
RAS.MAX
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
Speed Grade Definition Speed Bins for DDR2–667
Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400
t
t
REFI
REFI
.
.
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 3
@ CL = 4
@ CL = 5
Symbol
t
t
t
t
t
t
t
Symbol
t
t
t
t
t
t
t
V
V
CK
CK
CK
RAS
RC
RCD
RP
CK
CK
CK
RAS
RC
RCD
RP
REF
REF
V
V
stabilizes. During the period before
stabilizes. During the period before
TT
TT
.
.
DDR2–667C
–3
4–4–4
Min.
5
3
3
45
57
12
12
DDR2–533C
–3.7
4–4–4
Min.
5
3.75
3.75
45
60
15
15
28
HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A
Max.
8
8
8
70000
—
—
—
Max.
8
8
8
70000
—
—
—
Unbuffered DDR2 SDRAM Modules
DDR2–667D
–3S
5–5–5
Min.
5
3.75
3
45
60
15
15
DDR2–400B
–5
3–3–3
Min.
5
5
5
40
55
15
15
V
V
REF
REF
stabilizes, CKE = 0.2 x
stabilizes, CKE = 0.2 x
Max.
8
8
8
70000
—
—
—
Max.
8
8
8
70000
—
—
—
Electrical Characteristics
02182004-DHQB-4RRW
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
CK
CK
Rev. 1.3, 2005-09
V
V
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
DDQ
DDQ
is
is