hyb18t512160bf-5 Infineon Technologies Corporation, hyb18t512160bf-5 Datasheet - Page 34

• Manufacturer Part Number: hyb18t512160bf-5
• Description: 240-pin Unbuffered Ddr2 Sdram Modules
• Manufacturer: Infineon Technologies Corporation

4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS,
6) Inputs are not recognized as valid until
7) The output timing reference voltage level is
8) 0 ≤
9) 85 <
10) x4 & x8
11) x16
Table 24
Parameter
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data strobe)
DQ and DM input hold time (single-ended strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data strobe)
DQ and DM input setup time (single-ended strobe)
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data Sheet
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode
recognized as low.
T
T
CASE
CASE
≤ 85 °C
Timing Parameter by Speed Grade - DDR2-400
≤ 95 °C
V
REF
V
stabilizes. During the period before
TT
.
34
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH
CKE
CL
DAL
DELAY
DH
DH1
DIPW
DQSCK
DQSL,H
DQSQ
DQSS
DS
DS1
DSH
DSS
HP
HZ
IH
IPW
IS
LZ(DQ)
LZ(DQS)
MRD
OIT
QH
(base)
(base)
(base)
(base)
(base)
(base)
HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A
Unbuffered DDR2 SDRAM Modules
DDR2-400
Min.
–600
2
0.45
3
0.45
WR +
t
275
25
0.35
–500
0.35
—
– 0.25
150
25
0.2
0.2
MIN. (
—
475
0.6
350
2
t
2
0
t
IS
AC.MIN
HP
x
+
–
t
AC.MIN
t
t
CK
V
QHS
t
t
REF
CL,
RP
+
t
t
stabilizes, CKE = 0.2 x
IH
CH
)
Max.
+600
—
0.55
—
0.55
—
––
––
––
—
+500
—
350
+ 0.25
—
—
—
—
t
—
—
—
t
t
—
12
—
AC.MAX
AC.MAX
AC.MAX
Electrical Characteristics
02182004-DHQB-4RRW
Unit
ps
t
t
t
t
t
ns
ps
ps
t
ps
t
ps
t
ps
ps
t
t
ps
ps
t
ps
ps
ps
t
ns
Rev. 1.3, 2005-09
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
V
Note
1)2)3)4)5)6)7)
DDQ
is