hyb18t512160bf-5 Infineon Technologies Corporation, hyb18t512160bf-5 Datasheet - Page 32

• Manufacturer Part Number: hyb18t512160bf-5
• Description: 240-pin Unbuffered Ddr2 Sdram Modules
• Manufacturer: Infineon Technologies Corporation

Table 22
Parameter
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
1) For details and notes see the relevant INFINEON component data sheet
2)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
6) Inputs are not recognized as valid until
7) The output timing reference voltage level is
8) 0 ≤
9) 85 °C <
10) x4 & x8
11) x16
Table 23
Parameter
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data
strobe)
DQ and DM input hold time (single ended data
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
DQ and DM input setup time (single ended data
strobe)
DQS falling edge hold time from CK (write cycle)
Data Sheet
V
powered down and then restarted through the specified initialization sequence before normal operation can continue.
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode
recognized as low.
DDQ
T
CASE
= 1.8 V ± 0.1 V;
T
CASE
≤ 85 °C
Timing Parameter by Speed Grade - DDR2-667
Timing Parameter by Speed Grade - DDR2-533
≤ 95 °C
V
DD
= 1.8 V ± 0.1 V. See notes
V
REF
V
stabilizes. During the period before
TT
.
4)5)6)7)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH
CKE
CL
DAL
DELAY
DH
DH1
DIPW
DQSCK
DQSL,H
DQSQ
DQSS
DS
DS1
DSH
(base)
(base)
32
(base)
(base)
Symbol
t
t
XSNR
XSRD
HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A
DDR2–533
Min.
–500
2
0.45
3
0.45
WR +
t
225
–25
0.35
–450
0.35
—
WL – 0.25
100
–25
0.2
IS
Unbuffered DDR2 SDRAM Modules
+
t
DDR2-667
Min.
t
200
CK
RFC
t
RP
+
+10
V
t
IH
REF
stabilizes, CKE = 0.2 x
Max.
+500
—
0.55
—
0.55
—
––
––
—
—
+450
—
300
WL + 0.25
—
—
—
Electrical Characteristics
Max.
—
—
02182004-DHQB-4RRW
Rev. 1.3, 2005-09
Unit
ns
t
Unit
ps
t
t
t
t
t
ns
ps
ps
t
ps
t
ps
t
ps
ps
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
V
Note
3)4)5)6)7)
Note
1)2)3)4)5)6)
7)
DDQ
is
1)2)