hyb18t512160bf-5 Infineon Technologies Corporation, hyb18t512160bf-5 Datasheet - Page 38

• Manufacturer Part Number: hyb18t512160bf-5
• Description: 240-pin Unbuffered Ddr2 Sdram Modules
• Manufacturer: Infineon Technologies Corporation

Table 27
Parameter
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING.
All Bank Interleave Read Current
All banks are being interleaved at minimum
and address bus inputs are STABLE during DESELECTS.
1)
2)
3) Definitions for
4)
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode
6) For details and notes see the relevant INFINEON component data sheet
Table 28
Parameter
LOW
STABLE
FLOATING
SWITCHING
Data Sheet
V
I
I
level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to
HIGH.
DD
DD1
DDQ
specifications are tested after the device is properly initialized and
,
I
= 1.8 V ± 0.1 V;
DD4R
I
Definitions for I
and
DD
Description
V
inputs are stable at a HIGH or LOW level
inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address
and control signals, and inputs changing between HIGH and LOW every other data transfer (once
per cycle) for DQ signals not including mask or strobes
inputs are
Measurement Conditions (cont’d)
I
I
IN
DD
DD7
≤
see
current measurements are defined with the outputs disabled (
V
IL(ac).MAX
V
Table 28
DD
V
= 1.8 V ± 0.1 V
REF
DD
, HIGH is defined as
=
I
DD6
V
DDQ
current values are guaranteed up to
/2
t
RC
without violating
V
1)2)3)4)5)6)
IN
≥
38
V
IH(ac).MIN
I
out
HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A
= 0 mA.
t
RRD
I
Unbuffered DDR2 SDRAM Modules
using a burst length of 4. Control
DD
parameter are specified with ODT disabled.
T
CASE
I
OUT
of 85 °C max.
= 0 mA). To achieve this on module
Electrical Characteristics
02182004-DHQB-4RRW
Rev. 1.3, 2005-09
Symbol
I
I
I
DD6
DD7
DD2P