hyb18t512160bf-5 Infineon Technologies Corporation, hyb18t512160bf-5 Datasheet - Page 30

• Manufacturer Part Number: hyb18t512160bf-5
• Description: 240-pin Unbuffered Ddr2 Sdram Modules
• Manufacturer: Infineon Technologies Corporation

Table 21
Parameter
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-Precharge
Write recovery time for write with Auto-Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read command (slow
exit, lower power)
Exit precharge power-down to any valid command (other
than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
1) For details and notes see the relevant INFINEON component data sheet
2)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
6) Inputs are not recognized as valid until
7) The output timing reference voltage level is
8) 0 ≤
9) 85 °C <
10) x4 & x8
11) x16
Table 22
Parameter
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data strobe)
Data Sheet
V
powered down and then restarted through the specified initialization sequence before normal operation can continue.
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode
recognized as low.
DDQ
T
CASE
= 1.8 V ± 0.1 V;
T
CASE
≤ 85 °C
Timing Parameter by Speed Grade - DDR2-800
Timing Parameter by Speed Grade - DDR2-667
≤ 95 °C
V
DD
= 1.8 V ± 0.1 V. See notes
V
REF
V
stabilizes. During the period before
TT
. See Chapter 8 for the reference load for timing measurements.
4)5)6)7)
30
Symbol
t
t
t
t
WR
t
t
t
t
t
t
Symbol
t
t
t
t
t
t
t
t
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
AC
CCD
CH
CKE
CL
DAL
DELAY
DH
(base)
HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A
Unbuffered DDR2 SDRAM Modules
DDR2-800
Min.
7.5
0.35
0.40
15
t
7.5
2
8 – AL
2
t
200
DDR2-667
Min.
–450
2
0.45
3
0.45
WR +
t
175
WR
RFC
IS
+
/
t
+10
t
CK
V
CK
REF
t
RP
+
stabilizes, CKE = 0.2 x
t
IH
Electrical Characteristics
Max.
—
—
0.60
—
—
—
—
—
—
—
Max.
+450
—
0.55
—
0.55
—
––
––
02182004-DHQB-4RRW
Rev. 1.3, 2005-09
Unit
ns
t
t
ns
t
ns
t
t
t
ns
t
Unit
ps
t
t
t
t
t
ns
ps
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
V
Note
1)2)3)4)5)6)
7)
Note
1)2)3)4)5)6)
7)
DDQ
is