hyb18tc256160af-3.7 Infineon Technologies Corporation, hyb18tc256160af-3.7 Datasheet
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256-Mbit DDR2 SDRAM ...
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Edition 2005-07 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...
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... HYB18TC256160AF HYB18TC256160AF Revision History: 2005-07, Rev. 1.0 Page Subjects (major changes since last revision) initial document We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
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... Self-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.25 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.26 Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.26.1 No Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.26.2 Deselect Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.27 Input Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.28 Asynchronous CKE LOW Reset Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4 Truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . & DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM 4 41 Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... Definition Data Setup ( . . . . . . . . . . . . . . 8.3.4 Slew Rate Definition for Input and Data Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.3.5 Setup ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10 Product Namenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM and Hold Time ( ), differential Data Strobes 100 and Hold Time ( ...
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... Table 50 Speed Grade Definition Speed Bins for DDR2-533C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 51 Timing Parameter by Speed Grade - DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 52 Timing Parameter by Speed Grade - DDR2-533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 53 ODT AC Electrical Characteristics and Operating Conditions for DDR2-667 Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM ) . . . . . . . . . . . . . . . . . Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... Nomenclature Fields and Examples 109 Table DDR2 Memory Components 109 Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM 7 Rev. 1.0, 2005-07 ...
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... Active Power-Down Mode Entry and Exit after an Activate Command . . . . . . . . . . . . . . . . . . . . . 64 Figure 52 Active Power-Down Mode Entry and Exit Example after a Read Command . . . . . . . . . . . . . . . . . 65 Figure 53 Active Power-Down Mode Entry and Exit Example after a Write Command . . . . . . . . . . . . . . . . . 65 Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM 8 t Limit ...
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... Slew Rate Definition Tangent 103 Figure 74 Package Pinout PG-TFBGA-84 (top view 108 Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM 9 Rev. 1.0, 2005-07 ...
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... CK6 f @CL5 333 CK5 f @CL4 266 CK4 f @CL3 200 CK3 t 15 RCD RAS HYB18TC256160AF HYB18TC256160AF 1) –3.7 Unit DDR2–533 4–4–4 — – 266 MHz 266 MHz 200 MHz Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... Ordering Information Table 2 Ordering Information for RoHS compliant products Part Number Org. Speed HYB18TC256160AF–3S ×16 DDR2–667 5–5–5 HYB18TC256160AF–3.7 ×16 DDR2–533 4–4–4 1) CAS: Column Adress Strobe 2) RCD: Row Column Delay 3) RP: Row Precharge Note: For product nomenclature see ...
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... Note: All command are masked when CS is registered HIGH. CS provides for external rank selection on systems with multiple memory ranks considered part of the command code. 12 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Pin Configuration and Block Diagrams 3. The abbreviations used in the Pin#/Buffer must be maintained to this input. CKE must Rev ...
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... Mode SSTL Register Set commands. SSTL SSTL SSTL SSTL SSTL SSTL Address Signal 13 Note: 512 Mbit components – Note: 256 Mbit components SSTL Bank Address Bus 1:0 SSTL – 13 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Pin Configuration and Block Diagrams Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Signal 3:0 SSTL Note: Bi-directional data bus. DQ[3:0] for × for 8 components SSTL SSTL SSTL Data Signal 7:4 SSTL SSTL SSTL 14 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Pin Configuration and Block Diagrams × 4 components, DQ[7:0] Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... SSTL Read Data Strobe SSTL Read Data Strobe SSTL Data Strobe Upper Byte SSTL SSTL Data Strobe Lower Byte SSTL 15 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Pin Configuration and Block Diagrams × 16 components × 16, LDQS Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... Power Supply – Power Supply – Power Supply – Not Connected Note: No internal electrical connection is present – Not Connected 16 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Pin Configuration and Block Diagrams × 16 components and control × 8 components the data mask Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT. SSTL On-Die Termination Control 17 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Pin Configuration and Block Diagrams × 8 × 16 configuration ODT is applied to Rev ...
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... Pin Configuration for ×16 components, P-TFBGA-84 (top view) Figure 1 Notes 1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0] Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Pin Configuration and Block Diagrams 2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15: ...
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... Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes] 1) Refered to as ’colbits’ 2) Refered to as ’org’ colbits × org/8 [Bytes] 3) PageSize = 2 Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Pin Configuration and Block Diagrams 16-Mbit x 16 BA[1:0] 4 A10 / AP A[12:0] A[8: ...
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... Block Diagram 4 Mbit ×16 I/O ×4 Internal Memory Banks Figure 2 Notes × 1. 16Mb 16 Organisation with 13 Row, 2 Bank and 9 Column External Adresses Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Pin Configuration and Block Diagrams 2. This Functional Block Diagram is intended to facilitate user understanding of the operation of the 20 Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Pin Configuration and Block Diagrams 3. LDM, UDM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional LDQS and UDQS signals. 21 Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... In particular situations involving more than one Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM bank, enabling / disabling on-die termination, Power-Down entry / exit, timing restrictions during state transitions - among other things - are not captured in full detail ...
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... The DDR2 SDRAM is now ready for normal operation. PRE MRS REF REF ALL tRP tMRD tRFC tMRD min 200 Cycle DLL RESET 23 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description tIS ANY MRS EMRS EMRS CMD tRFC tMRD Follow OCD tOIT Flowchart OCD ...
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... Reset do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents. 24 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description ). MRS, EMRS and DLL MRD Rev. 1.0, 2005-07 ...
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... A13 and all “higher” address bits have to be set to 0 for MRD compatibility with other DDR2 memory products with higher memory densities. BA2, Bank Address BA1, Bank Address BA0, Bank Address A13, Address bit 13 PD, Fast exit PD, Slow exit 25 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... BT, Sequential BT, Interleaved BL BL (ns timing WR is determined by WR MIN 26 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description t (ns). The mode register must be programmed CK t and WR is determined by CK.MAX MAX Rev. 1.0, 2005-07 07212005-A7MT-J7NM t (in ns) WR ...
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... QOff, Output buffers disabled RDQS, Disable RDQS, Enable DQS, Enable DQS, Disable OCD, OCD calibration mode exit, maintain setting B OCD, Drive (1) B OCD, Drive (0) B OCD, Adjust mode B OCD, OCD calibration default B 27 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... Failing to wait for synchronization to occur may result in a violation of the DRAM outputs allows users to measure during Read operations, without including the output buffer current and external load currents. 28 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description parameters. ...
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... BA2, Bank Address BA1, Bank Address BA0, Bank Address A[13:8], Address bits 29 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Signaling DQS DQS differential DQS signals Hi-Z ...
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... The EMRS(3) is written by asserting low on CS, RAS, CAS, WE, BA2 and high on BA0 and BA1, while controlling the state of the address pins. BA2, Bank Address BA1, Bank Address BA0, Bank Address A[13:0], Address bits 30 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description ) (cont’ Rev. 1.0, 2005-07 ...
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... OCD Impedance Adjustment Flow Chart Note: MR should be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM command being issued. MRS should be set before entering OCD impedance adjustment and On Die Termination (ODT) should be carefully controlled depending on system environment ...
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... Decrease by 1 step NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Decrease by 1 step Illegal 32 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Pull-down driver strength NOP (no operation) NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step ...
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... DT1 driven out output drivers are turned-off mode exit” command. See NOP NOP NOP DQS high for Drive(1) DQS high for Drive(0) 33 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description NOP NOP EMRS(1) tWR OCD calibration mode exit t after “enter drive mode” command and all ...
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... Switch sw1, sw2 or sw3 are enabled by the ODT pin. Selection between sw1, sw2 or sw3 is determined by “Rtt (nominal)” in EMRS(1) address bits A6 & A2. Data Sheet HYB18TC256160AF–[3S/3.7] the ODT control pin. UDQS and LDQS are terminated only when enabled in the EMRS(1) by address bit A10 = 0. ...
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... ODT function has to be enabled in the EMRS(1) by address bits A6 and A2. EMRS(1) Address Bit A10 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description EMRS(1) Address Bit A11 Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... ODT turn off time min. ( starts to turn off the ODT resistance. ODT turn off time max. ( impedance. Both are measured from tAOFPDmax tAOFPDmin Rtt 36 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description AOND AOFD tAOF(max) . AOND ...
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... ANPD.MIN asynchronous timing parameters apply. T-4 T-3 T-2 tANPD (3 tck RTT tAOFD RTT tAOFPDmax t IS tAOND t IS tAONPDmax 37 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description t applied not ANPD.MIN T Synchronous timings apply Asynchronous timings apply Synchronous RTT timings apply Asynchronous ...
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... Data Sheet t is satisfied applied. If AXPD.MIN parameters apply tAXPD ODT t IS ODT Rtt ODT t IS ODT 38 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description t is not satisfied, asynchronous timing AXPD.MIN T8 T9 T10 t IS Rtt tAOFD tAOFPDmax t IS tAOND Rtt tAONPDmax Rev. 1.0, 2005-07 ...
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... Col. Addr. Row Addr. Read A Begins Posted CAS Bank B Activate Read B tCCD tRC Row Cycle Time (Bank A) 39 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description t is satisfied. Additive latencies RCD.MIN t , respectively. The minimum time interval The minimum time ...
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... For details see Chapter 3.20 Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 40 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description minimum of 2 CCD t CCD T6 T7 T12 Dout B2 ...
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... Write Bank Dout0 Dout1Dout2 Dout3 Dout4 Dout5 Dout6 Dout7 : and ( (RL - HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description t RCD.MIN period, the Read Latency is also defined Din0 Din1 ...
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... Read Bank A Bank Write Read Bank A Bank WTR 42 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Write Bank Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 PostCAS2 ...
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... Page size for all 256 Mbit components is 1 KByte 2. Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR or DDR components Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM the MR. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MR ...
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... DQSCK AC DQS DQS t RPRE t LZ Dout Dout t DQSQmax NOP NOP NOP HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description t RPST t HZ Dout Dout t DQSQmax NOP NOP NOP <= t DQSCK Dout A0 Dout A1 Dout A2 Dout A3 Rev. 1.0, 2005-07 ...
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... Dout A0 Dout A1 Dout A2 Dout ste Dout A0 Dout A1 45 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Dout A4 Dout A5 Dout A6 Dout ...
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... Data Sheet NOP NOP NOP Dout Posted CAS NOP NOP READ B Dout A0 Dout A1 Dout A2 Dout A3 46 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description NOP NOP NOP Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout NOP NOP NOP ...
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... Din Din Din NOP NOP NOP <= t DQSS DIN A0 DIN A1 DIN A2 47 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description analog timing parameter WR 5) and is not the programmed value for t WPST Din NOP NOP NOP Precharge Completion of ...
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... Posted CAS NOP NOP READ A AL=2 tWTR DIN A0 DIN A1 DIN A2 DIN WTR t expressed in clock cycles. The WTR 48 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description NOP Precharge NOP tRP tWR NOP NOP NOP CL=3 RL not a write recovery time ( WTR Rev ...
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... Data Sheet Posted CAS NOP NOP WRITE B DIN A0 DIN HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description NOP NOP NOP DIN B0 DIN B1 DIN B2 DIN B3 DIN A2 DIN ...
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... HIGH during a write burst coincident with the write data, the write data bit is not written to the memory. For ×8 components the DM function is disabled, when RDQS / RDQS are enabled by EMRS(1 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... Dout Din A0 Din A1 Din A2 Din A3 Din B0 Din B1 51 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description t starts with the rising clock after the Dout B2 Dout B3 Dout B4 ...
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... NOP Precharge NOP tRP Dout A0 Dout >=tRC t ≤ 2 CKs RTP 52 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Precharge Bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only All banks 2× clocks for operating RTP CK t ...
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... CKs t RTP NOP NOP Precharge >=tRC >=tRTP t ≤ 2 CKs RTP 53 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Precharge NOP NOP tRP Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout Bank A ...
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... CKs RTP Dout A0 Dout A1 > > 2 CKs t RTP 54 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description NOP NOP NOP tRP Dout A0 Dout A1 Dout A2 Dout ...
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... T4 NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN NOP NOP NOP DIN A0 DIN A1 DIN A2 55 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description t delay, as DDR2 analog timing WR Chapter 7) and is not the programmed NOP NOP NOP Completion of the Burst Write ...
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... The RAS precharge time ( RTP RP from the clock at which the Auto-Precharge begins. 2. The RAS cycle time ( activation has been satisfied. 56 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description For the time from Read RTP ...
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... CKs t RTP ≤ 2 CKs t RTP 57 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description tRP Dout A0 Dout A1 Dout A2 Dout A3 BR-AP5231 T5 T6 ...
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... CKs RTP NOP NOP NOP Auto-Precharge Begins tRTP CKs RTP 58 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description tRP Dout A4 Dout A5 Dout A6 Dout A7 Dout A2 Dout ...
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... Limit Completion of the Burst Write DIN A0 DIN A1 DIN A2 DIN HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description t ) has been satisfied from the previous bank RC t timing parameter is not violated DAL ...
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... For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge-all, issued to that bank. The precharge period is satisfied after command issued to that bank Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Minimum Delay between “From Command” to “To Command” ...
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... A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh command is 9 × 61 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Unit t t WTR ...
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... CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh Mode. 62 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description > ...
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... In power- down mode, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and all other input signals are “Don’t Care”. Power-down duration is limited by 9 times 63 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Tm Tn tis > ...
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... tIS tIS Active Active Power-Down Power-Down Exit Entry t t (“fast exit”) or XARD XARDS 64 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Chapter 7.2. Tn+1 Tn+2 V alid and tXARD or tXARDS *) Act.PD 0 (“slow exit”) depends on the programmed Rev ...
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... XARD XARDS tIS Precharge Power-Down Exit t t (“fast exit”) or XARD XARDS 65 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Tn Tn tIS tIS tXARD or tXARDS *) Active Active Power-Down Power-Down ...
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... WR Power-Down t t (“fast exit”) or XARD XARDS NOP NOP NOP Precharge Power-Down Exit 66 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Tn Tn tIS tXARD or tXARDS *) Active Active Power-Down Entry Exit (“slow exit”) depends on the programmed ...
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... HIGH at the rising edge of the clock Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. when CS is brought HIGH, the RAS, CAS, and WE signals become don’t care. 67 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description Tn Valid Command tXP ...
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... DRAM is ready to operate with the new clock frequency Tx Frequency Change occurs here before power-down exit 68 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description t t and have been satisfied the input RP AOFD Ty+2 Ty+3 Ty ...
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... On and Initialization, step 4 through 13). DRAM is ready for normal operation after the initialization sequence. See Chapter 7 for tdelay Clocks can be turned off after this point 69 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Functional Description t specification. DELAY stable clocks Rev. 1.0, 2005-07 ...
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... Chapter 3.19 Chapter 3.23 70 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Truth tables A[12:11] A10 A[9:0] BA1 BA OP Code Row Address BA Column L Column ...
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... AUTOREFRESH H Refer to the Command Truth Table V )” in Self Refresh and Power Down. However ODT must be driven REF t (200 clocks) is satisfied. XSRD Chapter 3.23 and 71 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Truth tables 2)3) 2) Action (N) Maintain Power-Down Maintain Self Refresh Entry Self Refresh Entry + ...
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... V –0 –0.5 to +2.3 SS –55 to +100 V may be equal to or less than 300 mV. REF Rating temperature range, the High temperature Self Refresh has to be CASE 72 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions Unit Note 1)2) V 1) 1)3) °C Unit Note 1)2)3)4) ° ...
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... DDQ and to test pin separately, then measure current IH(ac) IL(ac – ( )). IL(ac) IHac ILac V V < DDQ 73 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions Unit Max. 1.9 V 1.9 V 1.9 V 0.51 × DDQ DDQ V + 0.04 V REF and tied together. DD DDQ DDDL ...
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... REF V — – 0.250 REF Figure 60 IL(ac) Start of Rising Edge Input Timing delta (ac).MAX V REF delta TF 74 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions DDR2-667 & DDR2-800 Min. Max 0.125 + 0.3 REF DDQ V –0.3 – 0.125 REF V + 0.200 — ...
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... V V – required for switching. The minimum value is equal the transmitting device and DDQ V of the transmitting device and DDQ Crossing Point VIX or VOX SSTL18_3 75 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions Unit Note 1) + 0.3 — DDQ 2) + 0.6 — DDQ 3) + 0.6 V ...
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... DD V DDQ V between OUT 1.7 V; DDQ OUT with the load specified in IL(ac) IH(ac) 76 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions Unit between OUT 1) 3) and . They are used to test drive current capability V between 0 V and 280 mV. OUT SSTL_18 ...
Page 77
... T ), CASE CASE 77 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions 2) 3) Max. 0.00 –7.95 –15.90 –23.85 –31.80 –39.75 –47.70 –55.55 –62.95 –69.55 –75.35 –80.35 –84.55 –87.95 –90.70 –93.00 – ...
Page 78
... The driver characteristics evaluation conditions are Maximum 0 °C ( Data Sheet 2) Nominal Default low Nominal Default high 0.00 0.00 5.65 5.90 11.30 11.80 16.50 16.80 21.20 22.10 25.00 27.60 28.30 32.40 30.90 36.90 33.00 40.90 34.50 44.60 35.50 47.70 36.10 50.40 36.60 52.60 36.90 54.20 37.10 55.90 37.40 57.10 37.60 58.40 37.70 59.60 37.90 60.90 — — T CASE T CASE 78 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions 2) 3) Max. 0.00 7.95 15.90 23.85 31.80 39.75 47.70 55.05 62.95 69.55 75.35 80.35 84.55 87.95 90.70 93.00 95.05 97.05 99.05 101. 1.7 V, slow-slow process DDQ 1.8 V, typical process CASE DDQ 1.9 V, fast-fast process DDQ Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... If calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. 79 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
Page 80
... Nominal Low Nominal (18.75 Ohms) (18 ohms) 10.7 11.5 16.0 16.6 21.0 21 Nominal Low Nominal 3) (18.75 Ohms) (18 ohms) –10.7 –11.4 –16.0 –16.5 –21.0 –21 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions 2) Nominal High Nominal Maximum (17.25 Ohms) (15 Ohms) 11.8 13.3 17.4 20.0 23.0 27 1.7 V, any process CASE DDQ 1.8 V, any CASE DDQ ...
Page 81
... CASE CASE 81 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions 2) 3) Max. 0.00 –4.77 –9.54 –14.31 –19.08 –23.85 –28.62 –33.33 –37.77 –41.73 –45.21 –48.21 –50.73 –52.77 –54.42 –55.80 – ...
Page 82
... VDDQ to VOUT (V) 2) IBIS Target low IBIS Target high 0.00 0.00 3.24 4.11 6.25 8.01 9.03 11.67 11.52 15.03 13.66 18.03 15.41 20.61 16.77 22.71 17.74 24.35 18.83 25.56 18.80 26.38 19.06 26.90 19.23 27.24 19.35 27.47 19.46 27.64 19.56 27.78 19.65 27.89 19.73 27.97 19.80 28.02 — — 82 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions Minimum IBIS Target Low IBIS Target High Maximum 1 Max. 0.00 4.77 9.54 14.31 19.08 23.85 28.62 33.33 37.77 41.73 45.21 48.21 50.73 52.77 54.42 55.80 57.03 58.23 59.43 60. 1.7 V, slow-slow process CASE DDQ 1.8 V, typical process CASE DDQ 1.9 V, fast-fast process ...
Page 83
... VOUT to VSSQ (V) VOUT to VSSQ (V) DDR2-400 & DDR-2-533 Min. 1.0 — 1.0 — 2.5 — 83 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions Minimum Minimum Nominal Default Low IBIS Target Low No IBIS Target High Maximum Maximum 1,8 2 1,8 2 DDR2-667 DDR2-800 Max. Min. Max. Min. 2.0 1 ...
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... Voltage across clamp (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Data Sheet The V-I characteristics for pins with clamps is shown in Table 40. Minimum Power Clamp Minimum Ground Clamp Current (mA) Current (mA 0.1 0.1 1.0 1.0 2.5 2.5 4.7 4.7 6.8 6.8 9.1 9.1 11.0 11.0 13.5 13.5 16.0 16.0 18.2 18.2 21.0 21.0 84 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... Data Sheet DDR2-400 V 1. 1.33 SS Maximum Amplitude VDD VSS Maximum Amplitude Time (ns) DDR2-400 V 0.38 DDQ V 0.38 SSQ Maximum Amplitude VDDQ VSSQ Maximum Amplitude Time (ns) 85 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC & DC Operating Conditions DDR2-533 DD2-667 Unit 0.5 0.5 V 0.5 0.5 V 1.00 0.80 V.ns 1.00 0.80 V.ns Overshoot Area Undershoot Area DDR2-533 DD2-667 Unit 0.5 0.5 V ...
Page 86
... CKE is HIGH HIGH between valid RP RP(IDD interval, CKE is HIGH HIGH RFC RFC(IDD 7.8 µs interval, CKE is LOW and CS is HIGH REFI 86 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Measurement Specifications and Conditions Symbol Note I DD0 I DD1 RCD RCD(IDD) ...
Page 87
... OUT (IDD CKE is HIGH HIGH between valid RRD(IDD) I current measurements are defined in chapter IL(ac).MAX V IH(ac).MIN REF DDQ 87 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Measurement Specifications and Conditions Symbol Note I DD6 I DD7 -1 × RCD(IDD) CK(IDD) Rev. 1.0, 2005-07 07212005-A7MT-J7NM 1)2)3)4)5)6) 1)2)3)4)5)6)7) ...
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... DD4W 160 I 95 DD5B I 6 DD5D I 4 DD6 I 138 DD7 157 1) MRS(12)=0 2) MRS(12)= ≤ T ≤ 85°C CASE Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM I Measurement Specifications and Conditions DD -3.7 Unit DDR2 - 533 Max ...
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... Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval 1) ×4 & ×8 (1 KByte Page Size) 2) ×16 (2 KByte Page Size); not on 256M component Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM I Measurement Specifications and Conditions DD Symbol –3S DDR2– ...
Page 90
... See Table EMRS(1) State DDQ ODTO current DDQ ODTT HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM –3.7 Unit Notes DDR2–533 4–4– 3. 7 ...
Page 91
... See section 8 for the reference load for timing measurements. TT DDR2–533 –3.7 4–4–4 Symbol Min 3. 3. RAS RCD HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Electrical Characteristics Unit Note t CK Max. — 1)2)3) 1)2)3) 1)2)3) 1)2)3)4)5) 70000 ns 1)2)3)4) — ns 1)2)3)4) — ns 1)2)3)4) — ...
Page 92
... DDR2 device can operate without a refresh command which is RAS.MAX t equal REFI Data Sheet V stabilizes. During the period before REF V . See section 8 for the reference load for timing measurements HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Electrical Characteristics V V stabilizes, CKE = 0 REF DDQ Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
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... OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Electrical Characteristics Symbol DDR2-667 Min. Max. t –450 ...
Page 94
... REF V . See Chapter 8 for the reference load for timing measurements and and transitions occur in the same access time windows LZ RPRE HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Electrical Characteristics DDR2-667 Unit Min. Max. 7.5 — — ns 7.5 — 0.35 — ...
Page 95
... DS1 t DSH t DSS (base IPW t (base LZ(DQ) 95 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Electrical Characteristics where are the values for a single bank can be used. In “low active power-down XARD DDR2–533 Unit Min. Max. –500 +500 ...
Page 96
... XARDS XSNR RFC t 200 XSRD 3)4)5)6) V stabilizes. During the period before REF V . See Chapter 8 for the reference load for timing measurements HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Electrical Characteristics Unit Note 3)4)5)6) Max. 12 AC.MAX t — — QHS 400 ...
Page 97
... LZ RPRE HZ LZ parameter is not a device limit. The device operates with a greater value for this parameter, t has to be satisfied. XARDS 97 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Electrical Characteristics t refers to the application clock period and ). CH transitions occur in the same access time windows as ...
Page 98
... AC.MIN AC.MIN 8 t AOND t . AOFD Values Min AC.MIN AC.MIN 2.5 t AC.MIN AC.MIN 8 t AOND t . AOFD 98 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Electrical Characteristics Unit Max 0 AC.MAX AC.MAX AC.MAX ...
Page 99
... DQS – DQS = + 500 mV. Output Slew Rate is defined with the reference load according to verified by design and characterization, but not subject to production test. from CK – +250 – –500mV for falling edges. 99 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC Timing Measurement Conditions test conditions, generally a ...
Page 100
... DQS/DQS signals must be monotonic between V and IL(dc).MAX t ) with 100 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC Timing Measurement Conditions for a falling IH(dc) V DDQ V min IH(ac) V min IH(dc) V REF V ...
Page 101
... The DQS signal must be monotonic between V and IH(dc).MIN 101 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC Timing Measurement Conditions t ), Single-Ended Data Strobes DH1 V level to the single- IH(dc the end of its IH/L(ac) V level to the single-ended data ...
Page 102
... Slew Rate line between shaded ‘dc to derating value (see earlier than the actual signal from the dc level to level is used for derating value (see 102 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC Timing Measurement Conditions Figure t ) nominal Slew Rate for a rising signal is ...
Page 103
... Figure 73 Slew Rate Definition Tangent Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC Timing Measurement Conditions 103 Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
Page 104
... 104 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC Timing Measurement Conditions For Slew Rates IH(ac) IL(ac) Unit 1.0 V/ns ∆ t ∆ t ∆ +124 +210 +154 ...
Page 105
... 105 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC Timing Measurement Conditions Unit 1.0 V/ns ∆ ∆ ∆ +124 +247 +154 ps +119 +239 +149 ps ...
Page 106
... 106 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC Timing Measurement Conditions 1.0 V/ns 0.8 V/ns ∆ ∆ ∆ ∆ ∆ ∆ — ...
Page 107
... DS1 DS1 DH1 107 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM AC Timing Measurement Conditions 1.0 V/ns ∆ ∆ ∆ ∆ ∆ — — — ...
Page 108
... Package Dimensions Figure 74 Package Pinout PG-TFBGA-84 (top view) Data Sheet HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM 108 Package Dimensions Rev. 1.0, 2005-07 07212005-A7MT-J7NM ...
Page 109
... Values HYB 18 T 256 512 160 –2.5 –3 –3S –3.7 –5 109 HYB18TC256160AF–[3S/3.7] 256-Mbit DDR2 SDRAM Product Namenclature –3.7 Coding Constant SSTL_18 DDR2 256 M 512 ×4 ×8 x16 look up table First ...
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