hyb18tc256160af-3.7 Infineon Technologies Corporation, hyb18tc256160af-3.7 Datasheet - Page 10

• Manufacturer Part Number: hyb18tc256160af-3.7
• Description: Consumer Dram Ddr2
• Manufacturer: Infineon Technologies Corporation

256-Mbit DDR2 SDRAM
DDR2 SDRAM
1
This chapter gives an overview of the 256-Mbit DDR2 SDRAM product family and describes its main
characteristics.
1.1
The 256-Mbit DDR2 SDRAM offers the following key features:
•
•
•
•
•
•
•
•
•
Table 1
Product Type Speed Code
Speed Grade
max. Clock Frequency
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
Data Sheet
1.8 V
1.8 V
DRAM organisations with 4, 8 and 16 data
in/outputs
Double Data Rate architecture: two data transfers
per clock cycle, four internal banks for concurrent
operation
CAS Latency: (2), 3, 4, 5 and 6
Burst Length: 4 and 8
All speed grades faster than DDR2–400 comply
with DDR2–400 timing specifications
Differential clock inputs (CK and CK)
Bi-directional, differential data strobes (DQS and
DQS) are transmitted / received with data. Edge
aligned with read data and center-aligned with write
data.
DLL aligns DQ and DQS transitions with clock
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and
polybrominated biphenyl ethers.
±
±
0.1 V Power Supply
0.1 V (SSTL_18) compatible I/O
Overview
Features
Performance DDR2–800 and DDR2–667
@CL6
@CL5
@CL4
@CL3
f
f
f
f
t
t
t
t
CK6
CK5
CK4
CK3
RCD
RP
RAS
RC
–3S
DDR2–667 5–5–5
333
333
266
200
15
15
45
60
10
•
•
•
•
•
•
•
•
•
•
•
•
DQS can be disabled for single-ended data strobe
operation
Commands entered on each positive clock edge,
data and data mask are referenced to both edges of
DQS
Data masks (DM) for write data
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver impedance adjustment (OCD) and
On-Die-Termination (ODT) for better signal quality.
Auto-Precharge operation for read and write bursts
Auto-Refresh, Self-Refresh and power saving
Power-Down modes
Average Refresh Period 7.8 µs
Full and reduced Strength Data-Output Drivers
2KByte Page Size for ×16
Packages: PG-TFBGA-84 for ×16 components
RoHS Compliant Products
–3.7
DDR2–533 4–4–4
–
266
266
200
15
15
45
60
HYB18TC256160AF
HYB18TC256160AF
1)
07212005-A7MT-J7NM
Rev. 1.0, 2005-07
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns