hyb18tc256160af-3.7 Infineon Technologies Corporation, hyb18tc256160af-3.7 Datasheet - Page 40

• Manufacturer Part Number: hyb18tc256160af-3.7
• Description: Consumer Dram Ddr2
• Manufacturer: Infineon Technologies Corporation

3.15
After a bank has been activated, a read or write cycle
can be executed. This is accomplished by setting RAS
HIGH, CS and CAS LOW at the clock’s rising edge. WE
must also be defined at this time to determine whether
the access cycle is a read operation (WE HIGH) or a
write operation (WE LOW). The DDR2 SDRAM
provides a wide variety of fast access modes. A single
Read or Write Command will initiate a serial read or
write operation on successive clock cycles at data rates
of up to 533 Mb/sec/pin for main memory. The
boundary of the burst cycle is restricted to specific
segments of the page length. For example, the
16 Mbit x 4 I/O x 4 Bank chip has a page length of 512
operation (burst length = 4) the page length of 512
bits x 4 I/O each). The 4-bit burst operation will occur
entirely within one of the 128 segments (defined by
CA[8:0]) starting with the column address supplied to
Figure 14
CL = 3, AL = 0, RL = 3, BL = 4
Data Sheet
is divided into 128 uniquely addressable segments (4
bits (defined by CA[11, 9:0]).In case of a 4-bit burst
C M D
D Q S ,
D Q S
C K , C K
D Q
R E A D A
T0
Read and Write Commands and Access Modes
Read Timing Example
T1
N O P
tC C D
R E A D B
T2
T3
N O P
Dout A0
tC C D
Dout A1
R E A D C
T4
Dout A2
40
the device during the Read or Write Command (CA[11,
9:0]). The second, third and fourth access will also
occur within this segment, however, the burst order is a
function of the starting address, and the burst
sequence.In case of a 8-bit burst operation (burst
length = 8) the page length of 512 is divided into 64
uniquely addressable segments (8 bits x 4 I/O each).
The 8-bit burst operation will occur entirely within one
of the 64 segments (defined by CA[7:0]) beginning with
the column address supplied to the device during the
Read or Write Command (CA[11, 9:0]). A new burst
access must not interrupt the previous 4 bit burst
operation in case of BL = 4 setting. Therefore the
minimum CAS to CAS delay (
clocks for read or write cycles.For 8 bit burst operation
(BL = 8) the minimum CAS to CAS delay (
clocks for read or write cycles.Burst interruption is
allowed with 8 bit burst operation. For details see
Chapter 3.20.
Dout A3 Dout B0
T5
N O P
Dout B1
T6
N O P
Dout B2
HYB18TC256160AF–[3S/3.7]
Dout B3 Dout C0
256-Mbit DDR2 SDRAM
T7
N O P
Functional Description
t
07212005-A7MT-J7NM
CCD
Dout C1
) is a minimum of 2
Rev. 1.0, 2005-07
N O P
T12
Dout C2
t
Dout C3
CCD
RB
N O P
) is 4