hyb18tc256160af-3.7 Infineon Technologies Corporation, hyb18tc256160af-3.7 Datasheet - Page 100
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hyb18tc256160af-3.7
Manufacturer Part Number
hyb18tc256160af-3.7
Description
Consumer Dram Ddr2
Manufacturer
Infineon Technologies Corporation
Datasheet
1.HYB18TC256160AF-3.7.pdf
(110 pages)
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8.3
8.3.1
Address and control input setup time (
from the input signal crossing at the
rising signal and
device under test. Address and control input hold time
Figure 69
8.3.2
Data input setup time (
enabled MR[bit10]=0, is referenced from the input
signal crossing at the
strobe crosspoint for a rising signal, and from the input
signal crossing at the
strobe crosspoint for a falling signal applied to the
device under test.
DQS/DQS signals must be monotonic between
V
Figure 70
Data Sheet
IL(dc).MAX
and
Input and Data Setup and Hold Time
Definition for Input Setup (
Input Setup and Hold Time
Definition for Data Setup (
Data Setup and Hold Time (Differential Data Strobes)
V
IH(dc).MIN
V
IL(ac)
V
V
for a falling signal applied to the
t
IH(ac)
IL(ac)
. Data input hold time (
DS
DQS
DQS
) with differential data strobe
level to the differential data
level to the differential data
CK
CK
V
t
IS
IH(ac)
t
) is referenced
DS
t
IS
level for a
t
t
DH
t
DH
t
DS
t
IS
IH
) with
) and Hold Time (
) and Hold Time (
100
t
DS
t
(
V
signal applied to the device under test.
differential data strobe enabled MR[bit10]=0, is
referenced from the input signal crossing at the
level to the differential data strobe crosspoint for a
rising signal and
crosspoint for a falling signal applied to the device
under test.
DQS/DQS signals must be monotonic between
V
IS
t
IH
IL(dc)
IL(dc).MAX
) is referenced from the input signal crossing at the
t
t
DH
IH
level for a rising signal and
and
t
t
V
IH
DH
AC Timing Measurement Conditions
IH(dc).MIN
)
), differential Data Strobes
V
HYB18TC256160AF–[3S/3.7]
V
V
V
V
V
V
V
IH(dc)
DDQ
IH(ac)
IH(dc)
REF
IL(dc)
IL(ac)
SS
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF
IL(dc)
IL(ac)
SS
.
max
max
min
min
to the differential data strobe
256-Mbit DDR2 SDRAM
min
min
max
max
07212005-A7MT-J7NM
V
Rev. 1.0, 2005-07
IH(dc)
for a falling
V
IL(dc)
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