hyb18tc256160af-3.7 Infineon Technologies Corporation, hyb18tc256160af-3.7 Datasheet - Page 64
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hyb18tc256160af-3.7
Manufacturer Part Number
hyb18tc256160af-3.7
Description
Consumer Dram Ddr2
Manufacturer
Infineon Technologies Corporation
Datasheet
1.HYB18TC256160AF-3.7.pdf
(110 pages)
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Power-Down Entry
Active Power-down mode can be entered after an
Activate command. Precharge Power-down mode can
be entered after a Precharge, Precharge-All or internal
precharge command. It is also allowed to enter power-
mode after an Auto-Refresh command or MRS /
EMRS(1) command when
Active Power-down mode entry is prohibited as long as
a Read Burst is in progress, meaning CKE should be
kept HIGH until the burst operation is finished.
Therefore Active Power-Down mode entry after a Read
or Read with Auto-Precharge command is allowed after
RL + BL/2 is satisfied.
Power-Down Exit
The power-down state is synchronously exited when
CKE is registered HIGH (along with a NOP or Deselect
command). A valid, executable command can be
Figure 51
Note: Active Power-Down mode exit timing
Data Sheet
state in the MR, address bit A12.
Active Power-Down Mode Entry and Exit after an Activate Command
C KE
C K , C K
C M D
t
MRD
A ctivate
T0
is satisfied.
Power-Down
Active
Entry
T1
N O P
tIS
t
XARD
T2
N O P
(“fast exit”) or
64
N O P
Active Power-down mode entry is prohibited as long as
a Write Burst and the internal write recovery is in
progress. In case of a write command, active power-
down mode entry is allowed when WL + BL/2 +
satisfied.
In case of a write command with Auto-Precharge,
Power-down mode entry is allowed after the internal
precharge command has been executed, which is WL
+ BL/2 + WR starting from the write with Auto-
Precharge command. In this case the DDR2 SDRAM
enters the Precharge Power-down mode.
applied with power-down exit latency,
XARDS
latencies are defined in
Power-Down
t
, after CKE goes HIGH. Power-down exit
XARDS
Active
Exit
Tn
N O P
tIS
(“slow exit”) depends on the programmed
Tn+1
tXARD or
tXARDS *)
N O P
HYB18TC256160AF–[3S/3.7]
Chapter
C om m and
Tn+2
256-Mbit DDR2 SDRAM
V alid
Act.PD 0
Functional Description
07212005-A7MT-J7NM
7.2.
Rev. 1.0, 2005-07
t
XP
,
t
XARD
t
WTR
or
is
t
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