m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 100

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Figure 2.5.5. Serial interface special function-related registers (4)
UARTi special mode register 2 (i= 0 to 3)
UARTi special mode register 1 (i= 0 to 3)
b7
b7
b6
b6
b5
b5
page 91 of 354
b4
b4
b3
b3
b2
b2
b1
b1
b0
b0
Note 1: These bits are unavailable when SCLi is external clock.
Bit Symbol
Bit Symbol
Note 1: Only “0“ may be written
Note 2: UART0 Timer A3 underflow signal, UART1: Timer A4 underlfow signal,
ABSCS
SWC2
IICM2
ACSE
LSYN
SWC
SDHI
CSC
STC
IICM
ABC
BBS
ALS
SSS
Symbol
UiSMR2 (i=0 to 3) 03A6
Symbol
UiSMR (i=0 to 3)
UART2 :Timer A0 underflow signal.
I
select bit 2
Clock synchronous bit
SCL wait output bit
SDA output stop bit
UARTi initialize bit
SCL Wait
output bit 2
SDA output
inhibit bit
SCLL sync output
enable bit
Auto-clear
function select bit
of transmit enable
bit
2
Nothing is assigned. Write "0" when writing to this bit.
The values are indeterminate when read.
C mode
I
select bit
Arbitration lost
detecting flag
control bit
Bus busy flag
Bus collision
detect sampling
clock select bit
Transmit start
condition select
bit
Nothing is assigned. Write "0" when writing to this bit.
The values are indeterminate when read.
2
C mode
Bit Name
Bit Name
03A7
16
16
0 : Normal mode
1 : I
0 : Update per bit
1 : Update per byte
0 : STOP detected
1 : START detected
0 : Disabled
1 : Enabled
Set to “0”
Set to “0”
Set to “0”
(clock synchronous
, 0366
, 0367
serial I/O mode)
0 : NACK/ACK interrupt (DMA source-ACK)
1 : UART transfer/receive interrupt (DMA
0 : Disable
1 : Enable
0 : Disable
1 : Enable
0 : Disable
1 : Enable
0 : Disable
1 : Enable
0 : UARTi clock
1 : 0 output
0 : Disabled
1 : Enabled (high impedance)
2
Address
Address
C mode
Function
Transfer to receive buffer at the rising edge
of last bit of receive clock.
Receive interrupt occurs at the rising edge
of last bit of receive clock.
source-UART receive)
Transfer to receive buffer at the falling edge
of last bit of receive clock.
Receive interrupt occurs at the falling edge
of last bit of receive clock
16
16
, 0337
, 0336
16
16
, 0326
, 0327
Function
16
16
0 : Rising edge of
1 : Timer Ai underflow
0 : No auto clear function
1 : Auto clear when bus
0 : Ordinary
1 : Falling edge of RxDi
Set to “0”
Set to “0”
Set to “0”
Set to “0”
transfer clock
signal (Note 2)
collision occurs
When reset
2. Serial Interface Special Function
When reset
(UART mode)
Function
00
00
(Note 1)
(Note 1)
(Note 1)
16
16
(Note 1)
R W
R W