m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 197

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
(2) Bulk Transfer: Endpoints 1 to 4 Receive
When endpoints 1 to 4 OUT are used for bulk transfer, ISO bit of USB endpoint x(x=1 to 4) OUT
control and status register is set to “0” for bulk transfer setting.
Also, for initialization of toggle sequence bit in bulk transfer, set TOGGLE_INIT bit to “1” and initialize
PID to DATA0.
Set by using USB endpoint x OUT FIFO configuration register in order to enable double buffer mode
and continuous receive mode.
Set AUTO_CLR bit of USB endpoint x OUT control and status register to “1” in order to use the
AUTO_CLR function.
When one packet data (Note 1) is received in OUT FIFO, the OUT_BUF_STS1 and the OUT_BUF_STS0
flags of the corresponding EPxOCS are automatically updated. In single buffer mode (when double
buffer mode bit is “0”), these flags are updated from “00
updated as follows:
When the OUT token is received from the host CPU while SEND_STALL bit is set to “1”, STALL
response is automatically returned.
When there is a packet space in OUT FIFO, on receiving the OUT token from the host CPU in the
current data toggle sequence bit, the data are received and ACK response is returned. At this time,
the OUT FIFO status is updated (updates the OUT_BUF_STS1 and OUT_BUF_STS0 flags) and
data toggle sequence bit is toggled (DATA0
x OUT interrupt request occurs.
When there is a packet space in OUT FIFO, on receiving the OUT token from the host CPU in the
toggle which is different from the current data toggle sequence bit, it is regarded that the ACK having
responded for the packet previously received has dropped and, therefore, the host CPU has trans-
mitted the same data. Only ACK response, therefore, is returned without receiving the data.
When the OUT token is received from the host CPU while there are already data in OUT FIFO and
packet data cannot be received, NAK response is automatically returned.
When a packet, which size exceeds the maximum packet size, is transmitted from the host CPU,
STALL response automatically is returned without receiving the data. At this time, the
FORCE_STALL flag is set to “1” and, when error interrupt has been enabled by USB function inter-
rupt enable register, an error interrupt request occurs (INTST8 is set to “1”).
•When the first one packet data (Note 1) of the double buffer has been written to the OUT FIFO and
•When two packet data (Note 1) have been written in OUT FIFO, the OUT_BUF_STS1 and
Note 1: In continuous transfer enable, read the description by substituting the underlined part with
Setting of Transfer Type
Receive Operation
the second packet data (Note 1) is ready to be written, the OUT_BUF_STS1 and OUT_BUF_STS0
flags are updated from “00
OUT_BUF_STS0 flags are updated from “10
“buffer data”. The USB function control unit writes the receive data from the host PC in OUT
FIFO sequentially by one packet size (the maximum packet size set in the EPxOMP), re-
ceives continuously until one buffer full or a short packet is received.
page 188 of 354
2
” to “10
2
”.
2
DATA1 or DATA1
” to “11
2
”".
2
” to “11
2
”. In double buffer mode, they are
DATA0). Further, the endpoint
2. USB function