m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 214

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Table 2.8.4. Status on Endpoint 1 to 4 IN FIFOs
*1: Bits 6 to 9 of EPxIFC.
IN_BUF_STS1
(5) Precautions for Transmit
Rate Feedback Interrupt Transfer:
Be sure to confirm that there is a space in the IN FIFO before writing data to the IN FIFO in prepara-
tion for packet data to the IN FIFO.
The IN FIFO state is indicated by the IN_BUF_STS1 and the IN_BUF_STS0 flags. Based on these
flags states, determine the count of data packets set in the IN FIFO.
The IN FIFO status (IN_BUF_STS1 and IN_BUF_STS0 flags) is updated when transmit data are
prepared in the IN FIFO (SET_IN_BUF_RDY bit is set to “1”), when transmitting of one data to the
host CPU is completed, or when data inside the IN FIFO have been flushed (AUTO_FLUSH bit or
FLUSH bit has functioned.)
When TOGGLE_INIT bit is set to “1”, the read/write counter inside the FIFO is initialized. To initialize
the PID, set TOGGLE_INIT bit to “1” in the IN FIFO is empty state (the IN_BUF_STS0 and
IN_BUF_STS1 flags are “00
0
0
1
1
Writing to IN FIFO
PID Initialization
In real application, rate feedback interrupt transfer always has data to be transmitted to the host.
Therefore, the device does not repond with NAK to the IN token from the host in this transfer. On
receiving IN token from the host CPU, the IN FIFO data are always transmitted in the current data
sequence bit regardless of the IN_BUF_STS0 and IN_BUF_STS1 values. Except this point, the
transmit operation is the same as the normal interrupt transfer.
When IN token is received from the host CPU while SEND_STALL bit being set to “1”, STALL
response is automatically returned. On receiving IN token from the host CPU, the IN FIFO data are
transmitted in the current data sequence bit . On completing one data transmit (on receiving ACK
from the host CPU), the IN FIFO status is updated, data toggle sequence bit is toggled (DATA0
the normal interrupt transfer, the IN FIFO data are not deleted, which is retained until the next
packet data are updated. When one data transmit has not been unsuccessfully completed (an ACK
not received from the host CPU), the data are re-transmitted in the next IN token (the same data
are transmitted in the same toggle).
DATA1 or DATA1 DATA0), and the endpoint x IN interrupt request occurs. At this time, unlike
IN_BUF_STS0
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0
1
0
1
2
”).
[Specify IN FIFO size by the
BUF_SIZ
No data
Space equal to one buffer
Invalid
Invalid
One data set in the IN FIFO
No space in the IN FIFO
Single buffer
*1
]
(The number of bytes specified
by the BUF_SIZ
No data
Space equal to two buffer
Invalid
One data set in the IN FIFO
Space equal to one buffer
Two data set in the IN FIFO
No space in the IN FIFO
Double buffer [IN FIFO size =
*1
)
2. USB function
2]