tmp89fm42a TOSHIBA Semiconductor CORPORATION, tmp89fm42a Datasheet - Page 233

• Manufacturer Part Number: tmp89fm42a
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.4
Functions
RA005
14.4.8.3
supplied is fcgck/2 [Hz] (in NORMAL1/2 or IDLE1/2 mode) or fs/2
and a pulse width of two machine cycles or more is required at both the "H" and "L" levels.
double buffer is enabled by setting T01MOD<DBE1> to "0" or disabled by setting T01MOD<DBE1> to "1".
+00REG is read out, regardless of the T00MOD<DBE1> setting.
When an external source clock is selected, input the clock at the TC00 pin. The maximum frequency to be
The double buffer can be used for T01+00PWM and T01+00REG by setting T01MOD<DBE1>. The
When read instructions are executed on T01+00PWM and T01+00REG, the last value written into T01
Double buffer
・ When the double buffer is enabled
・ When the double buffer is disabled
T00REG, T01REG and T00PWM during the timer operation, the set values are first stored in the
double buffer, and T01+00PWM and T01+00REG are not updated immediately. T01+00PWM
and T01+00REG compare the previous set values with the up counter value. When a match be-
tween the up counter value and the T01+00REG set value is detected, an INTTC01 interrupt
request is generated and the double buffer set values are stored in T01+00PWM and T01+00REG.
Subsequently, the match detection is executed using new set values.
T00REG, T01REG and T00PWM while the timer is stopped, the set values are immediately stored
in both the double buffer and T01+00PWM and T01+00REG.
T00REG, T01REG and T00PWM during the timer operation, the set values are immediately stored
in T01+00PWM and T01+00REG. Subsequently, the match detection is executed using new set
values.
PPG1 pin is not reversed until the up counter overflows and a match detection is executed using
a new set value. If the value set to T01+00PWM or T01+00REG is equal to the up counter value,
the match detection is executed immediately after data is written into T01+00PWM and T01
+00REG. Therefore, the timing of changing the PPG1 pin may not be an integral multiple of the
source clock. If these are problems, enable the double buffer.
T00REG, T01REG and T00PWM while the timer is stopped, the set values are immediately stored
in T01+00PWM and T01+00REG.
When a write instruction is executed on T01PWM after write instructions are executed on
When a write instruction is executed on T01PWM after write instructions are executed on
When a write instruction is executed on T01PWM after write instructions are executed on
If the value set to T01+00PWM or T01+00REG is smaller than the up counter value, the
When a write instruction is executed on T01PWM after write instructions are executed on
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[Hz] (in SLOW1/2 or SLEEP1 mode),
TMP89FM42A