tmp89fm42a TOSHIBA Semiconductor CORPORATION, tmp89fm42a Datasheet - Page 91

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tmp89fm42a

Manufacturer Part Number
tmp89fm42a
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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4.2
Control
RA000
External interrupt control register 3
EINTCR3
(0x0FDA)
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear
Note 3: Interrupt requests may be generated when EINTCR3 is changed. Before doing such operation, clear the corresponding
Note 4: Bits 7 to 5 of EINTCR3 are read as "0".
INI3LVL
INT3ES
INT3NC
Read/Write
Bit Symbol
After reset
the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is
changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and
clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2,
wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NOR-
MAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt
latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/
fspl [s] after the operation mode is changed and clear the interrupt latch.
Noise canceller pass signal level
when the interrupt request signal is
generated for external interrupt 3
Selects the interrupt request gener-
ating condition for external interrupt
3
Sets the noise canceller sampling in-
terval for external interrupt 3
R
7
0
-
R
6
0
-
R
5
0
-
00 :
01 :
10 :
11 :
00 :
01 :
10 :
11 :
Page 72
0 :
1 :
Initial state or signal level "L"
Signal level "H"
An interrupt request is generated at the rising edge of the noise canceller
pass signal
An interrupt request is generated at the falling edge of the noise canceller
pass signal
An interrupt request is generated at both edges of the noise canceller pass
signal
Reserved
fcgck [Hz]
fcgck / 2
fcgck / 2
fcgck / 2
INT3LVL
NORMAL1/2, IDLE1/2
R
4
0
2
3
4
[Hz]
[Hz]
[Hz]
3
INT3ES
R/W
0
00 :
01 :
10 :
11 :
2
fs/4 [Hz]
fs/4 [Hz]
fs/4 [Hz]
fs/4 [Hz]
SLOW1/2, SLEEP1
1
TMP89FM42A
INT3NC
R/W
0
0

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