tmp89fm42a TOSHIBA Semiconductor CORPORATION, tmp89fm42a Datasheet - Page 43

• Manufacturer Part Number: tmp89fm42a
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.3
System clock controller
RA000
2.3.3.2
PINTWUC:
clock (fh) and inputs it to the timing generator.
changed.
changed.
frequency reference clock (fh) by 4.
Example: Switching the high-frequency reference clock from fc to fosc (warm-up time: approx. 100 μs = at fosc = 5 MHz)
(2)
The clock gear is a circuit that selects a gear clock (fcgck) obtained by dividing the high-frequency reference
Selects a divided clock at CGCR<FCGCKSEL>.
Two machine cycles are needed after CGCR<FCGCKSEL> is changed before the gear clock (fcgck) is
The gear clock (fcgck) may be longer than the set clock width, immediately after CGCR<FCGCKSEL> is
Immediately after reset release, the gear clock (fcgck) is set as fh/4, which is obtained by dividing the high-
Clock gear
Note:Don't change CGCR<FCGCKSEL> in the SLOW mode. This may stop the gear clock (fcgck) from being
consumption can be reduced.
changed.
The low-frequency reference clock (fs) is used to operate the TMP89FM42A at low speed. Power
Low-frequency reference clock (fs)
LD
LD
SET
SET
:
CLR
NOP
NOP
CLR
RETI
(WUCCR), 0y00000000
(WUCDR), 0x08
(EIRL).4
(SYSCR2). 7
:
(SYSCR1). 3
(SYSCR2). 6
Table 2-4 Gear Clock (fcgck)
CGCR<FCGCKSEL>
00
01
10
11
Page 24
;WUCCR<WUCDIV>←"00" (No division)
;WUCCR<WUCSEL>←"01" (Selects fosc as the source clock)
;Sets the warm-up time
;(Determine the time depending on the oscillator characteristics)
;100μs / 12.8 μs = 7.8 round up to 0x08
;Enables INTWUC interrupts
;SYSCR2<OSCEN>←"1"
;(Starts the internal high-frequency clock oscillation and starts the
warm-up counter)
SYSCR1<OSCSEL>←"0"
(Switches the high-frequency reference clock from fc to fosc)
Waits for 2 machine cycles
Waits for 2 machine cycles
SYSCR2<XEN>←"0" (Stops fc)
Reserved
fcgck
fh / 4
fh / 2
fh
TMP89FM42A