mc9s08sg4 Freescale Semiconductor, Inc, mc9s08sg4 Datasheet - Page 150
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mc9s08sg4
Manufacturer Part Number
mc9s08sg4
Description
8-bit Microcontroller Family
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S08SG4.pdf
(320 pages)
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Chapter 10 Internal Clock Source (S08ICSV2)
10.3.3
10.3.4
150
IREFST
CLKST
Field
TRIM
Field
3-2
7:0
7:5
4
Reset:
Reset:
POR:
POR:
W
W
R
R
ICS Trim Register (ICSTRM)
ICS Status and Control (ICSSC)
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
Reserved, should be cleared.
Internal Reference Status — The IREFST bit indicates the current source for the reference clock. The IREFST
bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock
domains.
0 Source of reference clock is external clock.
1 Source of reference clock is internal clock.
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00
01
10
11
Output of FLL is selected.
FLL Bypassed, Internal reference clock is selected.
FLL Bypassed, External reference clock is selected.
Reserved.
U
7
1
7
0
0
0
Table 10-5. ICS Status and Control Register Field Descriptions
Figure 10-6. ICS Status and Control Register (ICSSC)
Table 10-4. ICS Trim Register Field Descriptions
U
0
0
0
0
6
6
Figure 10-5. ICS Trim Register (ICSTRM)
MC9S08SG8 MCU Series Data Sheet, Rev. 3
U
0
0
0
0
5
5
IREFST
U
0
1
1
4
4
Description
Description
TRIM
U
0
0
0
3
3
CLKST
U
0
0
0
2
2
OSCINIT
Freescale Semiconductor
U
0
0
0
1
1
FTRIM
U
U
0
0
0
0
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