mc9s08sg4 Freescale Semiconductor, Inc, mc9s08sg4 Datasheet - Page 94
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mc9s08sg4
Manufacturer Part Number
mc9s08sg4
Description
8-bit Microcontroller Family
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S08SG4.pdf
(320 pages)
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Chapter 7 Central Processor Unit (S08CPUV2)
7.3.5
In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of
program memory after the opcode (high byte first).
7.3.6
Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and
two that use the stack pointer as the base reference.
7.3.6.1
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction.
7.3.6.2
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction. The index register pair is then incremented
(H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV
and CBEQ instructions.
7.3.6.3
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.4
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This
addressing mode is used only for the CBEQ instruction.
7.3.6.5
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.6
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit
offset included in the instruction as the address of the operand needed to complete the instruction.
94
Extended Addressing Mode (EXT)
Indexed Addressing Mode
Indexed, No Offset (IX)
Indexed, No Offset with Post Increment (IX+)
Indexed, 8-Bit Offset (IX1)
Indexed, 8-Bit Offset with Post Increment (IX1+)
Indexed, 16-Bit Offset (IX2)
SP-Relative, 8-Bit Offset (SP1)
MC9S08SG8 MCU Series Data Sheet, Rev. 3
Freescale Semiconductor
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