m30262f8gp Renesas Electronics Corporation., m30262f8gp Datasheet - Page 45
m30262f8gp
Manufacturer Part Number
m30262f8gp
Description
Renesas 16-bit Cmos Single-chip Microcomputer M16c Family / M16c/20 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.M30262F8GP.pdf
(239 pages)
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Status Transition of BCLK
Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.8.3 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0 (bit 6 at address
0006
from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset.
When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/
medium-speed mode is retained. The following shows the operational modes of BCLK.
(1) Division by 2 mode
(2) Division by 4 mode
(3) Division by 8 mode
(4) Division by 16 mode
(5) No-division mode
(6) Low-speed mode
(7) Low power dissipation mode
The main clock is divided by 2 to obtain the BCLK.
The main clock is divided by 4 to obtain the BCLK.
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
The main clock is divided by 16 to obtain the BCLK.
The main clock is divided by 1 to obtain the BCLK.
f
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
f
C
C
is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
is the BCLK and the main clock is stopped.
16
) and the X
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
IN
-X
OUT
drive capacity select bit (bit 5 at address 0007
Renesas Technology Corp.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16
) change to “1” when shifting
M16C/26 Group
39
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