r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1092
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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21. Serial Communication Interface with FIFO (SCIF)
21.3.9
SCFCR is a register that performs data count resetting and trigger data number setting for transmit
and receive FIFO registers, and also contains a loopback test enable bit.
SCFCR can always be read from and written to by the CPU.
Rev.1.00 Jan. 10, 2008 Page 1062 of 1658
REJ09B0261-0100
Initial value:
Bit
15 to 11
10
9
8
7
6
R/W:
BIt:
FIFO Control Register n (SCFCR)
Bit Name
—
RSTRG2*
RSTRG1*
RSTRG0*
RTRG1
RTRG0
15
⎯
R
0
14
⎯
R
0
1
1
1
13
⎯
R
0
Initial
Value
All 0
0
0
0
0
0
12
⎯
R
0
11
⎯
R
0
R/W
R
R/W
R/W
R/W
R/W
R/W
RG2*
R/W
RST
10
0
1
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SCIF_RTS Output Active Trigger
The SCIF_RTS signal becomes high when the number
of receive data stored in SCFRDR exceeds the trigger
setting count shown below.
000:63
001:1
010:8
011:16
100:32
101:48
110:54
111:60
Receive FIFO Data Count Trigger
These bits are used to set the number of receive data
bytes that sets the RDF flag in SCFSR.
The RDF flag is set when the number of receive data
bytes in SCFRDR is equal to or greater than the trigger
setting count shown below.
00:1
01:16
10:32
11:48
RG1*
R/W
RST
9
0
1
RG0*
R/W
RST
8
0
1
RTRG1
R/W
7
0
RTRG0
R/W
6
0
TTRG1
R/W
5
0
TTRG0
R/W
4
0
MCE*
R/W
3
0
1
TFCL
R/W
2
0
RFCL
R/W
1
0
LOOP
R/W
0
0
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