r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 903
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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19.3.18 Separation Width Register (SPWR)
The separation width register (SPWR) sets the low-level pulse width of the separation pulse for
the CSYNC signal. The value is retained during power-on reset and manual reset.
Internal update:
Internal update:
Bit
31 to 10 ⎯
9 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
SPW
31
15
—
—
R
R
0
0
30
14
—
—
R
R
0
0
Initial
Value
All 0
Undefined R/W
29
—
13
—
R
R
0
0
28
12
—
—
R
R
0
0
R/W
R
27
11
—
—
R
R
0
0
Internal
Update
⎯
Yes
26
10
—
—
R
R
0
0
R/W
25
—
—
O
R
0
9
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Separation Width
The low-level pulse width of the separation pulse
for the CSYNC signal should be set in dot clock
units.
The value set should be smaller than 1/2 the HC
bits in HCR.
To enable this setting, bit 1 of the CSY bits in
DSMR should be set to 1.
R/W
24
—
—
R
O
0
8
R/W
23
—
—
R
O
0
7
Rev.1.00 Jan. 10, 2008 Page 873 of 1658
R/W
22
—
—
R
O
0
6
R/W
21
—
—
O
R
0
5
SPW
R/W
20
—
—
O
R
0
4
R/W
19. Display Unit (DU)
19
—
—
R
O
0
3
REJ09B0261-0100
R/W
18
—
—
R
O
0
2
R/W
17
—
—
R
O
0
1
R/W
16
—
—
O
R
0
0
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