r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1151
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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Part Number:
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Bit
7 to 5
4 to 0
Bit Name
RFWM[2:0] 000
RFUA[4:0]
Initial
Value
00000
R/W
R/W
R
Description
Receive FIFO Watermark
000: Issue a transfer request when 1 stage or more of
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 4 or more stages of
101: Issue a transfer request when 8 or more stages of
110: Issue a transfer request when 12 or more stages
111: Issue a transfer request when 16 stages of the
•
•
Receive FIFO Usable Area
These bits indicate the number of words that can be
transferred by the CPU or DMAC as B'00000 (empty) to
B'10000 (full).
A transfer request to the receive FIFO is issued by
the RDREQE bit in SISTR.
The receive FIFO is always used as 16 stages of
the FIFO regardless of these bit settings.
the receive FIFO are valid.
the receive FIFO are valid.
the receive FIFO are valid.
of the receive FIFO are valid.
receive FIFO are valid.
Rev.1.00 Jan. 10, 2008 Page 1121 of 1658
22. Serial I/O with FIFO (SIOF)
REJ09B0261-0100
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