r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 655
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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(25) PCI Cache Snoop Control Register 1 (PCICSCR1)
An external device can access memory of this LSI via the PCIC. When an PCI device accesses a
cacheable area, the PCIC can issue cache snoop commands to the on-chip caches. This register can
specify the function that uses PCICSAR1. For details, see section 13.4.4 (7), Cache Coherency.
Initial value:
Initial value:
Bit
1, 0
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
Bit:
Bit:
Bit Name
SNPMD
31
15
—
—
—
—
R
R
0
0
30
14
—
—
—
—
R
R
0
0
Initial
Value
All 0
29
13
—
—
—
—
R
R
0
0
28
—
—
12
—
—
R
R
0
0
R/W
PCI: —
SH: R/W
27
—
—
11
—
—
R
R
0
0
26
10
—
—
—
—
R
R
0
0
Description
Snoop Mode for PCICSAR0
These bits specify whether PCICSAR0 is compared
with the SuperHyway bus address requested by an
external device, or not. When PCICSAR0 is specified
to be compared, a condition to issue snoop
commands can be specified.
00: PCICSAR0 is not compared
01: Reserved (setting prohibited)
10: PCICSAR0 is compared. If the address matches
11: PCICSAR0 is compared. If the address matches
25
—
—
—
—
R
R
0
9
0
PCICSAR0 in the range, snoop commands are
not issued. If not, snoop commands are issued.
PCICSAR0 in the range, snoop commands are
issued. If not, snoop commands are not issued.
24
—
—
—
—
R
R
0
8
0
23
—
—
—
—
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 625 of 1658
22
—
—
—
—
R
R
0
6
0
21
—
—
—
—
R
R
0
5
0
R/W
20
—
—
—
R
0
4
0
13. PCI Controller (PCIC)
RANGE
R/W
19
—
—
—
R
0
3
0
REJ09B0261-0100
R/W
18
—
—
—
R
0
2
0
R/W
17
—
—
—
R
0
1
SNPMD
0
R/W
16
—
—
—
R
0
0
0
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