m38039mf-xxxsp Mitsumi Electronics, Corp., m38039mf-xxxsp Datasheet - Page 72

• Manufacturer Part Number: m38039mf-xxxsp
• Description: Single-chip 8-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

[I
The I
ACK control, SCL mode and SCL frequency.
•Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 11.
•Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the
standard clock mode is selected. When the bit is set to “1,” the
high-speed clock mode is selected.
When connecting the bus of the high-speed mode I
dard (maximum 400 kbits/s), use 8 MHz or more oscillation
frequency f(X
•Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock is generated.
When this bit is set to “0,” the ACK return mode is selected and
SDA goes to “L” at the occurrence of an ACK clock. When the bit
is set to “1,” the ACK non-return mode is selected. The SDA is
held in the “H” status at the occurrence of an ACK clock.
However, when the slave address agree with the address data in
the reception of address data at ACK BIT = “0,” the SDA is auto-
matically made “L” (ACK is returned). If there is a disagreement
between the slave address and the address data, the SDA is auto-
matically made “H” (ACK is not returned).
•Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which is an ac-
knowledgment response of data transfer. When this bit is set to
“0,” the no ACK clock mode is selected. In this case, no ACK clock
occurs after data transmission. When the bit is set to “1,” the ACK
clock mode is selected and the master generates an ACK clock
each completion of each 1-byte data transfer. The device for
transmitting address data and control data releases the SDA at
the occurrence of an ACK clock (makes SDA “H”) and receives the
ACK bit generated by the data receiving device.
Note: Do not write data into the I
72
ACK clock: Clock for acknowledgment
2
C Clock Control Register (S2)] 0015
2
data is written during transfer, the I
that data cannot be transferred normally.
C clock control register (S2: address 0015
IN
) in the high-speed mode (2 division clock).
2
C clock control register during transfer. If
2
C clock generator is reset, so
16
) is used to set
2
C bus stan-
16
Fig. 66 Structure of I
Table 11 Set values of I
Notes 1: Duty of SCL output is 50 %. The duty becomes 35 to 45 % only
CCR4
0
0
0
0
0
0
0
1
1
1
b7
ACK
Setting value of
CCR3
2: Each value of SCL frequency exceeds the limit at
3: The data formula of SCL frequency is described below:
CCR4–CCR0
A C K
B I T
0
0
0
0
0
0
0
1
1
1
when the high-speed clock mode is selected and CCR value = 5
(400 kHz, at
–4 to +2 machine cycles in the standard clock mode, and fluctu-
ates from –2 to +2 machine cycles in the high-speed clock mode.
In the case of negative fluctuation, the frequency does not in-
crease because “L” duration is extended instead of “H” duration
reduction.
These are values when SCL synchronization by the synchronous
function is not performed. CCR value is the decimal notation
value of the SCL frequency control bits CCR4 to CCR0.
more. When using these setting value, use
Do not set 0 to 2 as CCR value regardless of
Set 100 kHz (max.) in the standard clock mode and 400 kHz
(max.) in the high-speed clock mode to the SCL frequency by
setting the SCL frequency control bits CCR4 to CCR0.
/(8
/(4
/(2
M O D E C C R 4 C C R 3 C C R 2 C C R 1 C C R 0
frequency
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
F A S T
CCR2
0
0
0
0
1
1
1
1
1
1
CCR value) Standard clock mode
CCR value) High-speed clock mode (CCR value
CCR value) High-speed clock mode (CCR value = 5)
CCR1
0
0
1
1
0
0
1
0
1
1
= 4 MHz). “H” duration of the clock fluctuates from
MITSUBISHI MICROCOMPUTERS
2
CCR0
C clock control register
0
1
0
1
0
1
0
1
0
1
2
C clock control register and SCL
Setting disabled
Setting disabled
Setting disabled
(at
500/CCR value
Standard clock
3803/3804 Group
– (Note 2)
– (Note 2)
b 0
(Note 3)
mode
= 4 MHz, unit : kHz) (Note 1)
17.2
16.6
16.1
83.3
100
I
( S 2 : a d d r e s s 0 0 1 5
S C L f r e q u e n c y c o n t r o l b i t s
R e f e r t o T a b l e 1 1 .
S C L m o d e s p e c i f i c a t i o n b i t
A C K b i t
A C K c l o c k b i t
2
C c l o c k c o n t r o l r e g i s t e r
SCL frequency
0 : S t a n d a r d c l o c k m o d e
1 : H i g h - s p e e d c l o c k m o d e
0 : A C K i s r e t u r n e d .
1 : A C K i s n o t r e t u r n e d .
0 : N o A C K c l o c k
1 : A C K c l o c k
High-speed clock
1000/CCR value
Setting disabled
Setting disabled
Setting disabled
of 4 MHz or less.
400 (Note 3)
frequency.
(Note 3)
mode
34.5
33.3
32.3
1 6
333
250
166
= 4 MHz or
)
5)