m38039mf-xxxsp Mitsumi Electronics, Corp., m38039mf-xxxsp Datasheet - Page 80

• Manufacturer Part Number: m38039mf-xxxsp
• Description: Single-chip 8-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

[I
0017
The I
trols special functions such as occurrence timing of reception
interrupt request and extending slave address comparison to 3
bytes.
•Bit 1: ACK interrupt control bit (ACKICON)
This bit controls the timing of I
completion of data receiving due to master reception or slave re-
ception.
When this bit is “0”, the SCL pin low hold bit (PIN) is set to “0” in
synchronization with the falling of the last SCL clock, including the
ACK clock. The SCL pin is simultaneously held low, and the I
interrupt request occurs.
When this bit is “1” and the ACK clock bit (ACK) is “1”, the SCL pin
low hold 2 flag (PIN2) is set to “0” in synchronization with the fall-
ing of the data’s last SCL clock, just before the ACK clock. The
SCL pin is simultaneously held low, and the I
occurs again. The ACK bit can be changed after the contents of
data are confirmed by using this function.
Fig. 76 Structure of I
80
2
C Special Mode Control Register (S3D)]
2
C special mode control register (S3D: address 0017
16
2
C special mode control register
2
C interrupt request occurrence at
S P F C L
b7
N o t e s 1 : D o n o t w r i t e “ 1 ” t o t h e s e b i t s s i m u l t a n e o u s l y .
PIN2-
HD
PIN2IN
2: r e t u r n “ 0 ” w h e n r e a d
2
C interrupt request
MS L A D
A C K I
C O N
b0
16
) con-
I
( S 3 D : a d d r e s s 0 0 1 7
2
ACK interrupt control bit
Slave address control bit
SCL pin low hold 2 flag set bit (Notes 1, 2)
STOP condition flag clear bit (Note 2)
Not used
(Fix this bit to “0”.)
Not used
(return “0” when read)
Not used
(Fix this bit to “0”.)
SCL pin low hold set bit (Notes 1, 2)
C s p e c i a l m o d e c o n t r o l r e g i s t e r
Writing “1” to this bit initializes the SCL pin low
hold 2 flag to “1”.
0 : At communication completion
1 : At falling of ACK clock and communication
0 : One-byte slave address compare mode
1 : Three-byte slave address compare mode
When writing “1” to this bit, the SCL pin low
hold 2 flag becomes “0” and the S
low.
Writing “1” to this bit initializes the STOP
condition flag to “0”.
2
C
completion
•Bit 2: I
This bit controls a slave address. When this bit is “0”, only the I
slave address register 0 (address 0FF7
slave address and a read/write bit.
When this bit is “1”, all of the I
(addresses 0FF7
and a read/write bit. In this case, when an address data agrees
with any one of the I
address comparison flag (AAS) is set to “1” and the I
dress comparison flag corresponding to the agreed I
address registers 0 to 2 is also set to “1”.
•Bit 5: SCL pin low hold 2 flag set bit (PIN2IN)
Writing “1” to this bit initializes the SCL pin low hold 2 flag (PIN2)
to “1”.
When writing “0”, nothing is generated.
•Bit 6: SCL pin low hold set bit (PIN2HD)
When the SCL pin low hold bit (PIN) becomes “0”, the SCL pin is
held low. However, the SCL pin low hold bit (PIN) cannot be set to
“0” by software. The SCL pin low hold set bit (PIN2HD) is used to ,
hold the SCL pin in the low state by software. When writing “1” to
this bit, the SCL pin low hold 2 flag (PIN2) becomes “0”, and the
SCL pin is held low. When writing “0”, nothing occurs.
•Bit 7: STOP condition flag clear bit (SPFCL)
Writing “1” to this bit initializes the STOP condition flag (SPCF) to
“0”.
When writing “0”, nothing is generated.
1 6
)
2
C slave address control bit (MSLAD)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CL
16
pin is held
to 0FF9
2
MITSUBISHI MICROCOMPUTERS
C slave address registers 0 to 2, the slave
16
3803/3804 Group
) become valid as a slave address
2
C slave address registers 0 to 2
16
) becomes valid as a
2
C slave ad-
2
C slave
2
C