m38039mf-xxxsp Mitsumi Electronics, Corp., m38039mf-xxxsp Datasheet - Page 79

• Manufacturer Part Number: m38039mf-xxxsp
• Description: Single-chip 8-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

[I
0012
The I
sists of the flags indicating I
mode, which is set by the I
address 0017
The stop condition flag is valid in all operating modes.
•Bit 0: Slave address 0 comparison flag (AAS0)
These flags indicate a comparison result of address data. These
flags are valid only when the slave address control bit (MSLAD) is
“1”.
In the 7-bit addressing format of the slave reception mode, the re-
spective slave address i (i = 0, 1, 2) comparison flags
corresponding to the I
“1” when an address data immediately after an occurrence of a
START condition agrees with the high-order 7-bit slave address
stored in the I
to 0FF9
In the 10-bit addressing format of the slave mode, the respective
slave address i (i = 0, 1, 2) comparison flags corresponding to the
I
compared with the 8 bits consisting of the slave address stored in
the I
first byte agrees.
These flags are initialized to “0” at reset, when the slave address
control bit (MSLAD) is “0”, or when writing data to the I
shift register (S0: address 0011
Fig. 75 Structure of I
2
Bit 1: Slave address 1 comparison flag (AAS1)
Bit 2: Slave address 2 comparison flag (AAS2)
C slave address registers are set to “1” when an address data is
2
C Special Mode Status Register (S3)]
2
2
C slave address registers 0 to 2 and the RWB bit, and the
C special mode status register (S3: address 0012
16
16
).
16
2
C slave address registers 0 to 2 (addresses 0FF7
).
2
2
C special mode status register
C slave address registers 0 to 2 are set to
2
C special mode control register (S3D:
2
C operating state in the I
16
).
SPCF
N o t e : I n o r d e r t h a t t h e l o w h o l d s t a t e o f t h e S C L p i n m a y r e l e a s e , i t i s
b 7
n e c e s s a r y t h a t t h e S C L p i n l o w h o l d 2 f l a g a n d t h e S C L p i n l o w
h o l d b i t ( P I N ) a r e “ 1 ” s i m u l t a n e o u s l y .
P I N 2
A A S 2
2
C special
A A S 1
16
2
C data
) con-
A A S 0
b 0
16
I
( S 3 : a d d r e s s 0 0 1 2
Sl a v e a d d r e s s 0 c o m p a r i s o n f l a g
Slave address 1 comparison flag
Sl a v e a d d r e s s 2 c o m p a r i s o n f l a g
S C L p i n l o w h o l d 2 f l a g
S T O P c o n d i t i o n f l a g
2
N o t u s e d
( r e t u r n “ 0 ” w h e n r e a d )
N o t u s e d
( r e t u r n “ 0 ” w h e n r e a d )
N o t u s e d
( r e t u r n “ 0 ” w h e n r e a d )
C s p e c i a l m o d e s t a t u s r e g i s t e r
0 : S C L p i n l o w h o l d
1 : S C L p i n l o w r e l e a s e ( N o t e )
0 : A d d r e s s d i s a g r e e m e n t
1 : A d d r e s s a g r e e m e n t
0 : Address disagreement
1 : Address agreement
0 : A d d r e s s d i s a g r e e m e n t
1 : A d d r e s s a g r e e m e n t
0 : N o d e t e c t i o n
1 : D e t e c t i o n
•Bit 5: SCL pin low hold 2 flag (PIN2)
When the ACK interrupt control bit (ACKICON) and the ACK clock
bit (ACK) are “1”, this flag is set to “0” in synchronization with the
falling of the data’s last SCL clock, just before the ACK clock. The
SCL pin is simultaneously held low, and the I
occurs.
This flag is initialized to “1” at reset, when the ACK interrupt con-
trol bit (ACKICON) is “0”, or when writing “1” to the SCL pin low
hold 2 flag set bit (PIN2IN).
The SCL pin is held low when either the SCL pin low hold bit (PIN)
or the SCL pin low hold 2 flag (PIN2) becomes “0”. The low hold
state of the SCL pin is released when both the SCL pin low hold
bit (PIN) and the SCL pin low hold 2 flag (PIN2) are “1”.
•Bit 7: Stop condition flag (SPCF)
This flag is set to “1” when a STOP condition occurs.
This flag is initialized to “0” at reset, when the I
enable bit (ES0) is “0”, or when writing “1” to the STOP condition
flag clear bit (SPFCL).
1 6
)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3803/3804 Group
2
C interrupt request
2
C-BUS interface
79